Pll Input Clock Source Select Register (Pll_Ifsr); Fclk Source Select Register (Fclk_Ssr) - Wiznet W7500 Reference Manual

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[0] PLLBP – bypass register of PLL

This bit written by S/W to control bypass or not of PLL

0 : bypass disable. Normal operation

1 : bypass enable. Clock out is clock input

10.4.6 PLL input clock source select register (PLL_IFSR)

Address offset : 0x020

Reset value : 0x0000_0000

[0] PLLIS – select register of PLL input clock source

This bit written by S/W to select

0 : Internal 8MHz RC oscillator clock (RCLK)

1 : External oscillator clock (OCLK, 8MHz ~ 24MHz)

Address offset : 0x030

Reset value : 0x0000_0001

[1:0] FCKSRC – select register of FCLK clock source

These bits are written by S/W to select

W7500 Datasheet Version1.0.0