Uart1Icr (Uart1 Interrupt Clear Register) - Wiznet W7500 Reference Manual

[2] DCDMMIS – nUART1DCD modem masked interrupt status
It indicates state of the UART1DCDINTR interrupt.
[1] CTSMMIS – nUART1CTS modem masked interrupt status
It indicates state of the UART1CTSINTR interrupt.
[0] RIMMIS – nUART1RI modem masked interrupt status
It indicates state of the UART1RIINTR interrupt.
22.6.13

UART1ICR (UART1 Interrupt Clear Register)

Address offset: 0x0044
Reset value: -
The UART1ICR register is the interrupt clear register and is write-only.
31 30 29 28
res res res res
15 14 13 12
res res res res
[10] OEIC – Overrun error interrupt clear
Clear the UART1OEINTR interrupt.
[9] BEIC – Break error interrupt clear
Clear the UART1BEINTR interrupt.
[8] PEIC – Parity error interrupt clear
Clear the UART1PEINTR interrupt.
[7] FEIC – Framing error interrupt clear
Clear the UART1FEINTR interrupt.
[6] RTIC – Receive timeout interrupt clear
Clear the UART1RTINTR interrupt.
[5] TXIC – Transmit interrupt clear
Clear the UART1TXINTR interrupt.
[4] RXIC – Receive interrupt clear
Clear the UART1RXINTR interrupt.
[3] DSRMIC – nUART1DSR modem interrupt clear
Clear the UART1DSRINTR interrupt.
[2] DCDMIC – nUART1DCD modem interrupt clear
Clear the UART1DCDINTR interrupt.
W7500 Datasheet Version1.0.0
27 26 25 24
res res res res
11 10 9
res
OEIC BEIC PEIC
R R
23 22 21
res res res
8 7 6 5
FEIC RTIC TXIC
R R R
R
20 19 18 17
res res res res
4 3 2 1
DSRM DCDM CTSM
RXIC
IC IC IC
R R R R
473 / 512
16
res
0
RI
MIC
R