Uart0Icr (Uart0 Interrupt Clear Register) - Wiznet W7500 Reference Manual

It indicates state of the UART0DSRINTR interrupt.
[2] DCDMMIS – nUART0DCD modem masked interrupt status
It indicates state of the UART0DCDINTR interrupt.
[1] CTSMMIS – nUART0CTS modem masked interrupt status
It indicates state of the UART0CTSINTR interrupt.
[0] RIMMIS – nUART0RI modem masked interrupt status
It indicates state of the UART0RIINTR interrupt.
22.4.13

UART0ICR (UART0 Interrupt Clear Register)

Address offset: 0x0044
Reset value: -
The UART0ICR register is the interrupt clear register and is write-only.
31 30 29 28
res res res res
15 14 13 12
res res res res
[10] OEIC – Overrun error interrupt clear
Clear the UART0OEINTR interrupt.
[9] BEIC – Break error interrupt clear
Clear the UART0BEINTR interrupt.
[8] PEIC – Parity error interrupt clear
Clear the UART0PEINTR interrupt.
[7] FEIC – Framing error interrupt clear
Clear the UART0FEINTR interrupt.
[6] RTIC – Receive timeout interrupt clear
Clear the UART0RTINTR interrupt.
[5] TXIC – Transmit interrupt clear
Clear the UART0TXINTR interrupt.
[4] RXIC – Receive interrupt clear
Clear the UART0RXINTR interrupt.
[3] DSRMIC – nUART0DSR modem interrupt clear
Clear the UART0DSRINTR interrupt.
[2] DCDMIC – nUART0DCD modem interrupt clear
Clear the UART0DCDINTR interrupt.
W7500 Datasheet Version1.0.0
27 26 25 24
res res res res
11 10 9 8
res
OEIC BEIC PEIC
R R
R
23 22 21
res res res
7 6 5
FEIC RTIC TXIC
R R R
20 19 18 17
res res res res
4 3 2 1
DSR DCD CTS
RXIC
MIC MIC MIC
R R R R
459 / 512
16
res
0
RI
MIC
R