Watchdog Timer Registers (Base Address : 0X4000_0000); Watchdog Timer Load Register(Wdtload); Watchdog Timer Value Register(Wdtvalue); Figure 44 Watchdog Timer Operation Flow Diagram - Wiznet W7500 Reference Manual

Users can mask interrupts by writing 0 to the Interrupt Enable bit in the control
register. Users can read the following from status registers:
Raw interrupt status, before masking.
-
Final interrupt status, after masking.
-
Watchdog timer is
programmed
20.4

Watchdog timer Registers (Base address : 0x4000_0000)

20.4.1 Watchdog timer Load Register(WDTLoad)

Address offset : 0x000
Reset value : 0xFFFF_FFFF
31
[31:0] WLR – Watchdog timer Load Register.
This register contains the value from which the counter is to decrement.
When this register is written to, the count is immediately restarted from
the new value. The minimum valid value for WDTLoad is 1.

20.4.2 Watchdog timer Value Register(WDTValue)

Address offset : 0x004
Reset value : 0xFFFF_FFFF
31
[31:0] WVR – Watchdog timer Value Register.
This register gives the current value of the decrementing counter.
W7500 Datasheet Version1.0.0
Count down
without reprogram
Counter reaches zero
If the interrupt enable bit in the
WDTControl register is set to 1,
interrupt is asserted.

Figure 44 Watchdog timer operation flow diagram

Counter reloaded
and count down
without reprotram
WDTControl register is set to 1, reset
WLR
R/W
WVR
R
Counter reaches zero
If the reset enable bit in the
request signal is asserted.
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