I2C1 Interrupt Status Mask Register(I2C1_Ismr) - Wiznet W7500 Reference Manual

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`[0]RST – interrupt reset

All interrupt is clear.

(TXE,RXE,TSR,BT)

[31:1] Reserved, must be kept at reset value

I2C1 Interrupt Status Mask Register(I2C1_ISMR)

Address offset: 0x28

Reset value: 0x0000_0000

[0]ACK_TXEM – Acknowledge Transmit status clear

Writing a 1 to this bit clears the ACK_TRANS bit in the I2C1_ISR register

Writing 0 has no effect

[1]ACK_RXEM – Acknowledge Receive status clear

Writing a 1 to this bit clears the ACK_RECV bit in the I2C1_ISR register

Writing 0 has no effect

[2]TOEM - Timeout interrupt clear

Writing a 1 to this bit clears the TO bit in the I2C1_ISR register

W7500 Datasheet Version1.0.0