Uart0Ris (Uart0 Raw Interrupt Status Register) - Wiznet W7500 Reference Manual

0: Disable UART0RXINTR
1: Enable UART0RXINTR
[3] DSRMIM – nUART0DSR modem interrupt mask
0: Disable UART0DSRINTR
1: Enable UART0DSRINTR
[2] DCDMIM – nUART0DCD modem interrupt mask
0: Disable UART0DCDINTR
1: Enable UART0DCDINTR
[1] CTSMIM – nUART0CTS modem interrupt mask
0: Disable UART0CRSINTR
1: Enable UART0CRSINTR
[0] RIMIM – nUART0RI modem interrupt mask
0: Disable UART0RIINTR
1: Enable UART0RIINTR
22.4.11

UART0RIS (UART0 Raw Interrupt Status Register)

Address offset: 0x003C
Reset value: 0x00-
The UART0RIS register indicates the raw interrupt status register.
31 30 29 28
res res res res
15 14 13 12
res res res res
[10] OERIS – Overrun error interrupt status
It indicates state of the UART0OEINTR interrupt.
[9] BERIS – Break error interrupt status
It indicates state of the UART0BEINTR interrupt.
[8] PERIS – Parity error interrupt status
It indicates state of the UART0PEINTR interrupt.
[7] FERIS – Framing error interrupt status
It indicates state of the UART0FEINTR interrupt.
[6] RTRIS – Receive timeout interrupt status
It indicates state of the UART0RTINTR interrupt.
[5] TXRIS – Transmit interrupt status
It indicates state of the UART0TXINTR interrupt.
W7500 Datasheet Version1.0.0
27 26 25 24
res res res res
11 10 9 8
OE BE PE
res
RIS RIS RIS
R R
R
23 22 21 20
res res res res
7 6 5 4
FE RT TX RX
RIS RIS RIS RIS
R R R R
19 18 17 16
res res res res
3 2 1 0
DRR DCD CTSR RI
RMIS RMIS MIS RMIS
R R R R
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