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Flash status register (FSTATR)
Flash lock register (FLOCKR0/R1)
Flash key register (FKEYR0/R1)
Unlocking the Flash access Control register (FACCR)
After reset, the Flash memory is protected against unwanted write or erase operations. The
FACCR register is not accessible in write mode. An unlocking sequence should be written to
the FKEYR0/R1 register to open the access to the FACCR register. This sequence consists of
two write operations:
Write KEY 0 (FKEYR0) = 0x52537175
Write KEY 1 (FKEYR1) = 0xA91875FC
Any wrong sequence locks up the FACCR register.
The FACCR register can be locked again by finishing flash control operation.
9.2.2
Read operations
The embedded Flash module can be addressed directly as a common memory space. Any
data read operation accesses the content of the Flash module through dedicated read senses
and provides the requested data.
The instruction fetch and the data access are both done through the same AHB bus. Read
accesses can be performed with the following options managed through the Flash control
register. (FCTRLR)
The Flash reading sequence using FCTRLR register is as below:
1. Check that no main Flash memory operation is ongoing by checking the RDY bit in
the FSTATR register.
2. Set KEY in FKEYR0/R1 for setting FACCR register.
3. Set FEN and CTRL bits in the FACCR register.
4. Write main Flash memory address or Data block address to FADDR register.
5. Set RDI or RD bit in FACTRLR to 1. If use RDI bit, don‟t need to set FADDR again due
to increase automatically by SZ bit in FACCR register.
6. Read data from FDATAR register.
7. Wait until the RDY bit is 1 in the FSTATR register.( it is set when the programming
operation has succeeded)
8. Set KEY in FKEYR0/R1 for clearing FACCR register.
9. Clear FEN and CTRL bits in the FACCR register
W7500 Datasheet Version1.0.0
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