Pause Register (Psr) - Wiznet W7500 Reference Manual

18.20.3

Pause Register (PSR)

Base address : 0x4000_5800
Address offset : 0x04
Reset value : 0x0000_0000
31 30 29 28
res res res res
15 14 13 12
res res res res
The Timer/Counter is paused after TC is reached to value of limit register.
[0] PS0 – Channel 0 Timer/Counter Pause.
0 : Timer/Counter is not paused.
1 : Timer/Counter is paused.
[1] PS1 – Channel 1 Timer/Counter Pause.
0 : Timer/Counter is not paused.
1 : Timer/Counter is paused.
[2] PS2 – Channel 2 Timer/Counter Pause.
0 : Timer/Counter is not paused.
1 : Timer/Counter is paused.
[3] PS3 – Channel 3 Timer/Counter Pause.
0 : Timer/Counter is not paused.
1 : Timer/Counter is paused.
[4] PS0 – Channel 4 Timer/Counter Pause.
0 : Timer/Counter is not paused.
1 : Timer/Counter is paused.
[5] PS0 – Channel 5 Timer/Counter Pause.
0 : Timer/Counter is not paused.
1 : Timer/Counter is paused.
[6] PS0 – Channel 6 Timer/Counter Pause.
0 : Timer/Counter is not paused.
1 : Timer/Counter is paused.
[7] PS0 – Channel 7 Timer/Counter Pause.
0 : Timer/Counter is not paused.
1 : Timer/Counter is paused.
W7500 Datasheet Version1.0.0
27 26 25 24
res res res res
11 10 9 8
res res res res
23 22 21 20
res res res res
7 6 5 4
PS7 PS6 PS5 PS4
R/W R/W R/W R/W
19 18 17 16
res res res res
3 2 1 0
PS3 PS2 PS1 PS0
R/W R/W R/W R/W
376 / 512