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7.6.9
Sn_TTLR (Socket n TTL Register) ................................................ 72
7.6.10
Sn_FRAGR (Socket n Fragment offset Register) ............................... 72
7.6.11
Sn_MSSR (Socket n Maximum Segment Register) .............................. 73
7.6.12
Sn_PORTR (Socket n Source Port Register) ..................................... 73
7.6.13
Sn_DHAR (Socket n Destination Hardware address Register) ............... 74
7.6.14
Sn_DPORTR (Socket n Destination Port Number Register) ................... 75
7.6.15
Sn_DIPR (Socket n Destination IP address Register) .......................... 75
7.6.16
Sn_KATMR (Socket n Keep Alive Timer Register) .............................. 76
7.6.17
Sn_RTR (Socket n Retry Time Register) ....................................... 77
7.6.18
Sn_RCR (Socket n Retry Counter Register) ..................................... 77
7.6.19
Sn_TXBUF_SIZE (Socket n TX Buffer Size Register) ........................... 78
7.6.20
Sn_TX_FSR (Socket n TX Free Size Register) ................................... 79
7.6.21
Sn_TX_RD (Socket n TX Read Pointer Register) ............................... 80
7.6.22
Sn_TX_WR (Socket n TX Write Pointer Register) .............................. 80
7.6.23
Sn_RXBUF_SIZE (Socket n RX Buffer Size Register) ........................... 81
7.6.24
Sn_RX_RSR (Socket n RX Received Size Register) ............................. 82
7.6.25
Sn_RX_RD (Socket n RX Read Pointer Register) ............................... 82
7.6.26
Sn_RX_WR (Socket n RX Write Pointer Register) .............................. 83
8 Booting Sequence ..................................................................................... 84
9 Embedded Flash memory ............................................................................ 85
9.1
Flash main features ........................................................................ 85
9.2
Flash memory functional description ................................................... 85
9.2.1
Flash memory organization ....................................................... 85
9.2.2
Read operations ..................................................................... 87
9.2.3
Flash erase operations ............................................................. 88
9.2.4
Flash program operation .......................................................... 90
9.3
Memory protection ......................................................................... 91
9.3.1
Read protection ..................................................................... 91
9.3.2
Write protection .................................................................... 91
10 Clock Reset generator (CRG) ........................................................................ 92
10.1
Introduction ................................................................................. 92
10.2
Features ..................................................................................... 92
10.2.1
Reset .................................................................................. 92
10.2.2
Clock .................................................................................. 92
10.3
Functional description .................................................................... 93
10.3.1
External Oscillator Clock .......................................................... 93
10.3.2
RC oscillator clock .................................................................. 94
10.3.3
PLL .................................................................................... 94
10.3.4
Generated clock .................................................................... 94
W7500 Datasheet Version1.0.0
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