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The counter generates an interrupt at a constant interval, reloading the original
value after wrapping past zero.
19.3.5
Interrupt
An interrupt is generated when the counter reaches 0 and is only cleared when the interrupt
clear register is accessed.
The register holds the value until the interrupt is cleared.
Users can mask interrupts by writing 0 to the Interrupt Enable bit in the control register.
Users can read the following from status registers:
Raw interrupt status before masking.
Final interrupt status after masking.
The interrupts from the individual timers after masking are logically ORed into a combined
interrupt.
19.3.6
Operation
The operation of each timer is identical. The timer is loaded by writing to the load register
and counts down to 0 if enabled. When a counter is already running, writing to the load
register causes the counter to immediately restart at the new value. Writing to the
background load value has no effect on the current count. In periodic mode, the counter
continues to decrease to 0 and restart from the new load value.
An interrupt is generated when 0 is reached. Users can clear the interrupt by writing to the
clear register. If users select one-shot mode, the counter halts when it reaches 0 until users
deselect one-shot mode or write a new load value.
Otherwise, after reaching a zero count, if the timer is operating in free-running mode, it
continues to decrease from its maximum value. If users select periodic mode, the timer
reloads the count value from the load register and continues to decrease. In this mode, the
counter effectively generates a periodic interrupt.
W7500 Datasheet Version1.0.0
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