Wiznet W7500 Reference Manual page 19

19.10.1 Timer1_0 Load Register(DUALTIMER1_0TimerLoad) ......................... 394
19.10.2 Timer1_0 Value Register(DUALTIMER1_0TimerValue)........................ 394
19.10.3 Timer1_0 Control Register(DUALTIMER1_0TimerControl) ................... 394
19.10.4 Timer1_0 Interrupt Clear Register (DUALTIMER1_0TimerIntClr) ........... 395
19.10.5 Timer1_0 Raw Interrupt Status Register (DUALTIMER1_0TimerRIS) ....... 395
19.10.6 Timer1_0 Masked Interrupt Status Register (DUALTIMER1_0TimerMIS) .. 396
19.10.7 Timer1_0 Background Load Register (DUALTIMER1_0TimerBGLoad) ...... 396
19.11 Register map ............................................................................... 398
19.12 Dual timer1_1 Registers (Base address : 0x4000_2020) ............................ 399
19.12.1 Timer1_1 Load Register(DUALTIMER1_1TimerLoad) ......................... 399
19.12.2 Timer1_1 Value Register(DUALTIMER1_1TimerValue)........................ 399
19.12.3 Timer1_1 Control Register(DUALTIMER1_1TimerControl) ................... 399
19.12.4 Timer1_1 Interrupt Clear Register (DUALTIMER1_1TimerIntClr) ........... 400
19.12.5 Timer1_1 Raw Interrupt Status Register (DUALTIMER1_1TimerRIS) ....... 400
19.12.6 Timer1_1 Masked Interrupt Status Register (DUALTIMER1_1TimerMIS) .. 401
19.12.7 Timer1_1 Background Load Register (DUALTIMER1_1TimerBGLoad) ...... 401
19.13 Register map ............................................................................... 403
19.14 Dual Timer 1 Clock Enable Register (Base address : 0x4000_2080) .............. 404
19.14.1 Timer1_0 Clock Enable Register (TIMCLKEN1_0) ............................. 404
19.14.2 Timer1_1 Clock Enable Register (TIMCLKEN1_1) ............................. 404
19.15 Register map ............................................................................... 405
20 Watchdog timer ...................................................................................... 406
20.1 Introduction ................................................................................ 406
20.2 Features .................................................................................... 406
20.3 Functional description ................................................................... 406
20.3.1 Clock ................................................................................. 406
20.3.2 Interrupt and reset request ...................................................... 406
20.4 Watchdog timer Registers (Base address : 0x4000_0000) .......................... 407
20.4.1 Watchdog timer Load Register(WDTLoad) ..................................... 407
20.4.2 Watchdog timer Value Register(WDTValue) ................................... 407
20.4.3 Watchdog timer Control Register(WDTControl) .............................. 408
20.4.4 Watchdog timer Interrupt Clear Register (WDTIntClr) ...................... 408
20.4.5 Watchdog timer Raw Interrupt Status Register (WDTRIS) .................. 408
20.4.6 Watchdog timer Raw Interrupt Status Register (WDTMIS) .................. 409
20.4.7 Watchdog timer Lock Register(WDTLock) ..................................... 409
20.5 Register map ............................................................................... 411
21 Inter-integrated circuit interface (I2C) ......................................................... 412
21.1 Introduction ................................................................................ 412
21.2 Features .................................................................................... 412
W7500 Datasheet Version1.0.0
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