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Figure 66 shows the timing diagram for both a single transfer request, and a burst transfer
request, with the appropriate DMA clear signal. The signals are all synchronous to PCLK.
PCLK
DMASREQ
DMABREQ
DMACLR
23.3.6
Interface reset
The PrimeCell SSP is reset by the global reset signal, PRESETn, and a block-specific reset
signal, nSSPRST. An external reset controller must use PRESETn to assert nSSPRST
asynchronously and negate it synchronously to SSPCLK. PRESETn must be asserted LOW for a
period long enough to reset the slowest block in the on-chip system, and then taken HIGH
again. The PrimeCell SSP requires PRESETn to be asserted LOW for at least one period of
PCLK.
23.3.7
Configuring the SSP
The Following reset, the PrimeCell SSP logic is disabled and must be configured when in this
state.
It is necessary to program control registers SSPCR0 and SSPCR1 to configure the peripheral as
a master or slave operating under one of the following protocols:
• Motorola SPI
• Texas Instruments SSI
• National Semiconductor.
The bit rate, derived from the external SSPCLK, requires the programming of the clock
prescale register SSPCPSR.
W7500 Datasheet Version1.0.0
Figure 66. DMA transfer waveforms
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