Watchdog Timer Raw Interrupt Status Register (Wdtmis); Watchdog Timer Lock Register(Wdtlock) - Wiznet W7500 Reference Manual

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[0] RIS – Watchdog timer Raw Interrupt Status.

This register indicates the raw interrupt status from the counter. This value

is ANDed with the interrupt enable bit from the control register to create

the masked interrupt, that is passed to the interrupt output pin.

20.4.6 Watchdog timer Raw Interrupt Status Register

Address offset : 0x014

Reset value : 0x0000_0000

[0] MIS – Watchdog timer Masked Interrupt Status.

This register indicates the masked interrupt status from the counter. This

value is the logical AND of the raw interrupt status with the interrupt

enable(IEN) bit from the control register, and is the same value that is

passed to the interrupt output pin.

Address offset : 0xC00

Reset value : 0x0000_0000

This register disables write accesses to all other registers. This is to prevent rogue

software from disabling the watchdog functionality. Writing a value of 0x1ACCE551

W7500 Datasheet Version1.0.0