Synchronous Serial Port (Ssp); Introduction; Features - Wiznet W7500 Reference Manual

23

Synchronous Serial Port (SSP)

23.1

Introduction

The SSP block is an IP provided by ARM (PL022 "PrimeCell® Synchronous Serial Port").
Additional details about its functional blocks may be found in "ARM PrimeCell® Synchronous
Serial Port (PL022) Technical Reference Manual".
23.2

Features

•
The SSP is a master or slave interface that enables synchronous serial communication
with slave or master peripherals having one of the following:
A MOTOROLA SPI-compatible interface

 A TEXAS INSTRUMENTS synchronous serial interface
A National Semiconductor MICROWIRE® interface.

•
The SPI interface operates as a master or slave interface. It supports bit rates up to 2
MHz and higher in both master and slave configurations. The SPI has the following
features:
 Parallel-to-serial conversion on data written to an internal 16-bit wide, 8-
location deep transmit FIFO
Serial-to-parallel conversion on received data, buffering it in a 16-bit wide, 8-

location deep receive FIFO
Programmable data frame size from 4 to 16 bits

Programmable clock bit rate and prescaler. The input clock may be divided by a

factor of 2 to 254 in steps of two to provide the serial output clock
Programmable clock phase and polarity.

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