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22.1
Introduction ................................................................................ 442
22.2
Features .................................................................................... 442
22.3
Functional description ................................................................... 442
22.3.1
Baud rate calculation ............................................................. 444
22.3.2
Data transmission .................................................................. 445
22.3.3
Data receive ........................................................................ 445
22.3.4
Hardware flow control ............................................................ 446
22.4
UART0 Registers(Base address: 0x4000_C000) ....................................... 448
22.4.1
UART0DR (UART0 Data Register) ................................................ 448
22.4.2
22.4.3
UART0FR (UART0 Flag Register) ................................................. 449
22.4.4
UART0ILPR (UART0 IrDA Low-Power Counter Register) ..................... 450
22.4.5
UART0IBRD (UART0 Integer Baud Rate Register) ............................. 451
22.4.6
UART0FBRD (UART0 Fractional Baud Rate Register) ......................... 451
22.4.7
UART0LCR_H (UART0 Line Control Register) .................................. 452
22.4.8
UART0CR (UART0 Control register) ............................................. 454
22.4.9
UART0IFLS (UART0 Interrupt FIFO Level Select Register) .................. 455
22.4.10
UART0IMSC (UART0 Interrupt Mask Set/Clear Register) .................... 456
22.4.11
UART0RIS (UART0 Raw Interrupt Status Register)............................ 457
22.4.12
UART0MIS (UART0 Masked Interrupt Status Register) ....................... 458
22.4.13
UART0ICR (UART0 Interrupt Clear Register) .................................. 459
22.5
Register map ............................................................................... 461
22.6
UART1 Registers(Base address: 0x4000_D000) ....................................... 462
22.6.1
UART1DR (UART1 Data Register) ................................................ 462
22.6.2
22.6.3
UART1FR (UART1 Flag Register) ................................................. 463
22.6.4
UART1ILPR (UART1 IrDA Low-Power Counter Register) ..................... 464
22.6.5
UART1IBRD (UART1 Integer Baud Rate Register) ............................. 465
22.6.6
UART1FBRD (UART1 Fractional Baud Rate Register) ......................... 465
22.6.7
UART1LCR_H (UART1 Line Control Register) .................................. 466
22.6.8
UART1CR (UART1 Control register) ............................................. 468
22.6.9
UART1IFLS (UART1 Interrupt FIFO Level Select Register) .................. 469
22.6.10
UART1IMSC (UART1 Interrupt Mask Set/Clear Register) .................... 470
22.6.11
UART1RIS (UART1 Raw Interrupt Status Register)............................ 471
22.6.12
UART1MIS (UART1 Masked Interrupt Status Register) ....................... 472
22.6.13
UART1ICR (UART1 Interrupt Clear Register) .................................. 473
22.7
Register map ............................................................................... 475
23 Synchronous Serial Port (SSP) .................................................................... 476
23.1
Introduction ................................................................................ 476
W7500 Datasheet Version1.0.0
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