Pb_05 Pad Control Register; Pb_06 Pad Control Register - Wiznet W7500 Reference Manual

0 : Low driving strength
1 : High driving strength
[5] PB04_IE : Input buffer enable selection register of Pad PB_04
0 : Input buffer disable
1 : Input buffer enable
[6] PB04_CS – CMOS input or Summit trigger input selection register of Pad PB_04
0 : CMOS input buffer
1 : Summit trigger input buffer
14.4.22
Address offset : 0x054
Reset value : 0x0000_0030
31 30 29 28
res res res res
15 14 13 12 11
res res res res
res
[1:0] PB05_PUPD – Pull-up, Pull-down selection register of Pad PB_05
These bits are written by S/W.
00 : Neither
01 : pull-down
10 : pull-up
11 : Neither
[2] PB05_DS – Driving strength selection register of Pad PB_05
0 : Low driving strength
1 : High driving strength
[5] PB05_IE : Input buffer enable selection register of Pad PB_05
0 : Input buffer disable
1 : Input buffer enable
[6] PB05_CS – CMOS input or Summit trigger input selection register of Pad PB_05
0 : CMOS input buffer
1 : Summit trigger input buffer
14.4.23
Address offset : 0x058
Reset value : 0x0000_0030
W7500 Datasheet Version1.0.0

PB_05 pad control register

27 26 25
res res res
10 9 8 7
res res res res

PB_06 pad control register

24 23 22 21
res res res res
6 5
PB05_CS PB05_IE
R/W R/W
20 19 18
res res res
4 3 2
res res PB05_DS PB05_PUPD
R/W
205 / 512
17 16
res res
1 0
R/W