Functional Description; 10.3.1 External Oscillator Clock; Table 7 External Oscillator Clock Sources; Figure 10 Crg Block Diagram - Wiznet W7500 Reference Manual

Two Timer clocks (TIMCLK0, TIMCLK1)

 8ea PWM clocks (PWMCLK0 - PWMCLK7)
Real time clock (RTCCLK)

WDOG clock (WDOGCLK)

 Random number generator clock (RNGCLK)
RNGCLK have only one source (pll output) and no prescaler
Some of the generated clocks turn off automatically when CPU enters sleep mode.
 ADCCLK, RNGCLK
Generate two Hardware TCPIP Clocks (MII_RXC, MII_TXC) are from external PADs.
Hardware TCPIP Clocks can be gated by register control.
All clocks generated from CRG can be monitored.
10.3

Functional description

Figure 10 shows the CRG block diagram.
CRG
OSC_IN
(8~24)MHz
OSC
OSC_OUT
8MHz
RC
RSTn
POR

10.3.1 External Oscillator Clock

External oscillator clock (OCLK) can be generated from two possible clock source
External crystal/ceramic resonator (8 to 24MHz external oscillator)

User external clock


Table 7 shows the two clock sources of external oscillator clock
W7500 Datasheet Version1.0.0
OCLK
SCLK
FIN FOUT
RCLK
PLL
ResetN
(to Reset gen.)

Figure 10 CRG block diagram

Table 7 External oscillator clock sources

External clock
MCLK
MCLK
RCLK
OCLK
OFF
MCLK
RCLK
OCLK
MCLK
OFF
MCLK
RCLK
OCLK
OFF
MCLK
RCLK
OCLK
OFF
/1,2,4,8,16,32,64,128
/1,2,4,8,16,32,64,128
FCLK
OFF
MCLK
/1,2,4,8,16,32,64,128
/1,2,4,8,16,32,64,128
RCLK
/1,2,4,8,16,32,64,128
OCLK
OFF
/1,2,4,8,16,32,64,128
FCLK
/1,2,4,8 FCLK
/1,2,4,8 ADCCLK
/1,2,4,8 SSPCLK
/1,2,4,8 UARTCLK
TIMCLK0/TIMCLK1
PWMCLK0 - PWMCLK7
WDOGCLK
Crystal/
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