Ssp0 Registers (Base Address : 0X4000_A000); Ssp0 Control Register 0 (Ssp0Cr0) - Wiznet W7500 Reference Manual

23.4

SSP0 Registers (Base Address : 0x4000_A000)

This section describes the SSP0 registers.
23.4.1

SSP0 Control register 0 (SSP0CR0)

Address offset: 0x0000
Reset value: 0x0000_0000
31 30 29 28
res res res res
15 14 13 12
SCR
R/W
[3:0] DSS – Data size select:
0000 : reserved, undefined operation
0001 : reserved, undefined operation
0010 : reserved, undefined operation
0011 : 4-bit data
[5:4] FRF – Frame Format
00 : Motorola SPI frame format
01 : TI synchronous serial frame format
10 : National Microwire frame format
11 : Reserved, undefined operation
[6] SPO – SSPCLKOUT polarity
This is applicable to Motorola SPI frame format only.
[7] SPH – SSPCLKOUT phase
This is applicable to Motorola SPI frame format only.
[15:8] SCR – Serial clock rate
The value SCR is used to generate the transmit and receive bit rate of the SSP. The
bit rate is:
fSSPCLK / (CPSDVR * (1 + SCR))
where
CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and
SCR is a value from 0-255.
W7500 Datasheet Version1.0.0
27 26 25 24
res res res res
11 10 9 8
SPH
R/W
23 22 21 20
res res res res
7 6 5 4
SPO FRF
R/W R/W
19 18 17 16
res res res res
3 2 1 0
DSS
R/W
496 / 512