Channel-1 Match Register (Pwmch1Mr); Channel-1 Limit Register (Pwmch1Lr) - Wiznet W7500 Reference Manual

15 14 13 12
res res res res
[5: 0] PR – Prescale Register
Prescale register. The PC is incremented when the PC is reached to the PR.
18.6.7

Channel-1 Match Register (PWMCH1MR)

Base address : 0x4000_5100
Address offset : 0x18
Reset value : 0x0000_0000
31
[31:0] MR – Match Register
Match register. The MR can generate a match interrupt and PWM output
waveform becomes 0 when the TC is reached to the MR. Match register
should be smaller than limit register(LR). If not, match interrupt is not
occurred and PWM output waveform is always 1.
18.6.8

Channel-1 Limit Register (PWMCH1LR)

Base address : 0x4000_5100
Address offset : 0x1C
Reset value : 0x0000_0000
31
[31:0] LR – Limit Register
Limit Register. The LR can generate an overflow interrupt and PWM output
waveform becomes 1 when the TC is reached to the LR. Match register
should be smaller than limit register(LR). If not, match interrupt is not
occurred and PWM output waveform is always 1.
W7500 Datasheet Version1.0.0
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MR
R/W
LR
R/W
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PR
R/W
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