Uart0Imsc (Uart0 Interrupt Mask Set/Clear Register) - Wiznet W7500 Reference Manual

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[2:0] TXIFLSEL – Transmit interrupt FIFO level select

UART0IMSC (UART0 Interrupt Mask Set/Clear Register)

Address offset: 0x0038

Reset value: 0x00

The UART0IMSC register is the interrupt mask set/clear interrupts. When a bit of UART0IMSC

is „1‟ and the corresponding bit of interrupt register is „1‟, an interrupt will be issued.

In other words, if a bit of UART0IMSC is „0‟, an interrupt will not be issued even if the

corresponding bit of interrupt register is „1‟.

[10] OEIM – Overrun error interrupt mask

0: Disable UART0OEINTR

1: Enable UART0OEINTR

[9] BEIM – Break error interrupt mask

0: Disable UART0BEINTR

1: Enable UART0BEINTR

[8] PEIM – Parity error interrupt mask

0: Disable UART0EINTR

1: Enable UART0EINTR

[7] FEIM – Framing error interrupt mask

0: Disable UART0FEINTR

1: Enable UART0FEINTR

[6] RTIM – Receive timeout interrupt mask

0: Disable UART0RTINTR

1: Enable UART0RTINTR

[5] TXIM – Transmit interrupt mask

0: Disable UART0TXINTR

1: Enable UART0TXINTR

[4] RXIM – Receive interrupt mask

W7500 Datasheet Version1.0.0