Interrupt; Figure 35 The Pwm Output Up To Match Register; Figure 36 The Pwm Output Up To Limit Register - Wiznet W7500 Reference Manual

PWMCLK
Start/Stop
Register
Timer/Counter
PWM output
Match Interrupt
Match
register
PWMCLK
Start/Stop
Register
Timer/Counter 3
PWM output
Overflow

Interrupt

Limit
register
If match register is set as 0, the PWM output will be 1 while the Timer/Counter is 0.
If the match register is bigger than the limit register, the PWM output is always 1.
18.3.4 Interrupt
The PWM has 8-bit interrupt enable register(IER) and each bit of IER corresponds to each
interrupt of channel. Each PWM channel has Channel-n Interrupt Enable register(CHn_IER).
The CHn_IER includes three types of interrupt: match, overflow, and capture. The match
interrupt occurs when the Timer/Counter is reached to value of match register. The overflow
interrupt occurs when the Timer/Counter is reached to value of limit register. The capture
interrupt occurs when external input is entered for capture.
W7500 Datasheet Version1.0.0
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Figure 35 The PWM output up to match register

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Figure 36 The PWM output up to limit register

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3
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7
4
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