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18.9
Register map
The following Table 23 summarizes the PWM Channel-2 registers.
Offset
Register
PWMCH2IR
0x00
reset value
PWMCH2IER
0x04
reset value
PWMCH2ICR
0x08
reset value
PWMCH2TCR
0x0C
0
0
0
reset value
PWMCH2PCR
0x10
reset value
PWMCH2PR
0x14
reset value
PWMCH2MR
0x18
0
0
0
reset value
PWMCH2LR
0x1C
1
1
1
reset value
PWMCH2UDMR
0x20
reset value
PWMCH2TCMR
0x24
reset value
PWMCH2PEEER
0x28
reset value
PWMCH2CMR
0x2C
reset value
PWMCH2CR
0x30
reset value
0
0
0
PWMCH2PDMR
0x34
reset value
PWMCH2DZER
0x38
reset value
PWMCH2DZCR
0x3C
reset value
W7500 Datasheet Version1.0.0
Table 23 PWM channel 2 register map and reset values
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
TCR
0
0
0
0
0
0
0
0
0
0
0
MR
0
0
0
0
0
0
0
0
0
0
0
LR
1
1
1
1
1
1
1
1
1
1
1
CR
0
0
0
0
0
0
0
0
0
0
0
DZC
0
0
0
0
비고
Channel-2 interrupt register
0
0
0
Channel-2 interrupt enable register
0
0
0
Channel-2 interrupt clear register
Write only register
Channel-2 Timer/Counter Register
0
0
0
0
0
0
Channel-2 Prescale Counter
PCR
Register
0
0
0
0
0
0
PR
Channel-2 Prescale Register
0
0
0
0
0
0
Channel-2 Match Register
0
0
0
0
0
0
Channel-2 Limit Register
1
1
1
1
1
1
Channel-2 Up-Down Mode Register
0
Channel-2 Timer/Counter Mode
TCM
Register
0
0
Channel-2 PWM output Enable and
PEEE
External input Enable Register
0
0
Channel-2 Capture Mode Register
0
Channel-2 Capture Register
0
0
0
0
0
0
Channel-2 Periodic Mode Register
0
Channel-2 Dead Zone Enable
Register
0
Channel-2 Dead Zone Counter
Register
0
0
0
0
0
0
328 / 512
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