Ssp0 Clock Prescale Register (Ssp0Cpsr); Ssp0 Interrupt Mask Set Or Clear Register (Ssp0Imsc) - Wiznet W7500 Reference Manual

1 : SSP is currently transmitting and/or receiving a frame or the transmit
FIFO is not empty.
23.4.5

SSP0 Clock prescale register (SSP0CPSR)

Address offset: 0x0010
Reset value: 0x0000_00000
31 30 29 28
res res res res
15 14 13 12
res res res res
[7:0] CPSDVSR – Clock prescale divisor
This must be an even number from 2-254, depending on the frequency of SSPCLK.
The least significant bit always returns zero on reads.
23.4.6

SSP0 Interrupt mask set or clear register (SSP0IMSC)

Address offset: 0x0014
Reset value: 0x0000_00000
31 30 29 28
res res res res
15 14 13 12
res res res res
[0] RORIM – Receive overrun interrupt mask:
0 : Receive FIFO written to while full condition interrupt is masked.
1 : Receive FIFO written to while full condition interrupt is not masked.
[1] RTIM – Receive timeout interrupt mask:
0 : Receive FIFO not empty and no read prior to timeout period interrupt is
masked.
W7500 Datasheet Version1.0.0
27 26 25 24
res res res res
11 10 9 8
res res res res
27 26 25 24
res res res res
11 10 9 8
res res res res
23 22 21 20
res res res res
7 6 5 4
CPSDVSR
R/W R/W R/W R/W
23 22 21 20
res res res res
7 6 5 4
res res res res
19 18 17 16
res res res res
3 2 1 0
R/W R/W R/W R/W
19 18 17 16
res res res res
3 2 1 0
TXI RXI RTI ROR
M M M IM
R/W R/W R/W R/W
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