Hardware Flow Control; Figure 62. Hardware Flow Control Description; Figure 63. Cts Functional Timing - Wiznet W7500 Reference Manual

22.3.4

Hardware flow control

UARTx
RX FIFO
and
flow control
TX FIFO
and
flow control
The RTS flow control is enabled by setting the RTSen of UARTxCR. If RTS is enabled, the data
flow is controlled as follows.
When the receiver FIFO level reaches the programmed trigger level, nUARTRTS(pin) is
asserted(to a high value). nUARTRTS is reasserted(to a low level) once the receiver FIFO has
reached the previous trigger level. The reasserted of nUARTRTS signals to the sending UART
to continue transmitting data.
The CTS flow control is enabled, the transmitter can only transmit data when nUARTCTS is
asserted. When nUARTCTR is de-asserted(to a low) the transmitter sends the next byte. To
stop the transmitter from sending the following byte, nUARTCTS must be released before the
middle of the last stop bit that is currently being sent.
UARTx_TX
start
nUARTCTS
W7500 Datasheet Version1.0.0
nUARTRTS
nUARTCTS

Figure 62. Hardware flow control description

stop
bit0..7

Figure 63. CTS Functional Timing

another UARTx
nUARTRTS
flow control
flow control
nUARTCTS
bits0..7 stop
start
RX FIFO
and
TX FIFO
and
start bits0..7 stop
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