Uart0Mis (Uart0 Masked Interrupt Status Register) - Wiznet W7500 Reference Manual

[4] RXRIS – Receive interrupt status
It indicates state of the UART0RXINTR interrupt.
[3] DSRRMIS – nUART0DSR modem interrupt status
It indicates state of the UART0DSRINTR interrupt.
[2] DCDRMIS – nUART0DCD modem interrupt status
It indicates state of the UART0DCDINTR interrupt.
[1] CTSRMIS – nUART0CTS modem interrupt status
It indicates state of the UART0CTSINTR interrupt.
[0] RIRMIS – nUART0RI modem interrupt status
It indicates state of the UART0RIINTR interrupt.
22.4.12

UART0MIS (UART0 Masked Interrupt Status Register)

Address offset: 0x0040
Reset value: 0x00-
The UART0MIS register is the masked interrupt status register.
31 30 29 28
res res res res
15 14 13 12
res res res res
[10] OEMIS – Overrun error masked interrupt status
It indicates state of the UART0OEINTR interrupt.
[9] BEMIS – Break error masked interrupt status
It indicates state of the UART0BEINTR interrupt.
[8] PEMIS – Parity error masked interrupt status
It indicates state of the UART0PEINTR interrupt.
[7] FEMIS – Framing error masked interrupt status
It indicates state of the UART0FEINTR interrupt.
[6] RTMIS – Receive timeout masked interrupt status
It indicates state of the UART0RTINTR interrupt.
[5] TXMIS – Transmit masked interrupt status
It indicates state of the UART0TXINTR interrupt.
[4] RXMIS – Receive masked interrupt status
It indicates state of the UART0RXINTR interrupt.
[3] DSRMMIS – nUART0DSR modem masked interrupt status
W7500 Datasheet Version1.0.0
27 26 25 24
res res res res
11 10 9 8
OE BE PE
res
MIS MIS MIS
R R
R
23 22 21 20
res res res res
7 6 5 4
FE RT TX RX
MIS MIS MIS MIS
R R R R
19 18 17 16
res res res res
3 2 1 0
DRR DCD CTS RI
MMIS MMIS MMIS MMIS
R R R R
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