Timer0_1 Masked Interrupt Status Register (Dualtimer0_1Timermis); Timer0_1 Background Load Register (Dualtimer0_1Timerbgload) - Wiznet W7500 Reference Manual

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Table of Contents

Address offset : 0x10

Reset value : 0x0000_0000

[0] RIS – Raw Interrupt Status Register

This register indicates the raw interrupt status from the counter. This value

is ANDed with the timer interrupt enable bit from the Timer Control Register

to create the masked interrupt, that is passed to the interrupt output pin.

Timer0_1 Masked Interrupt Status Register

(DUALTIMER0_1TimerMIS)

Base address : 0x4000_1020

Address offset : 0x14

Reset value : 0x0000_0000

[0] MIS – Masked Interrupt Status Register

This register indicates the masked interrupt status from the counter. This

value is the logical AND of the raw interrupt status with the timer interrupt enable

bit from the Timer Control Register, and is the same value that is passed to the

interrupt output pin.

Timer0_1 Background Load Register

(DUALTIMER0_1TimerBGLoad)

Base address : 0x4000_1020

Address offset : 0x18

Reset value : 0x0000_0000

W7500 Datasheet Version1.0.0