Uart0Cr (Uart0 Control Register) - Wiznet W7500 Reference Manual

22.4.8

UART0CR (UART0 Control register)

Address offset: 0x0030
Reset value: 0x0300
The UART0CR register is the control register
31 30 29
res res res
15 14 13
CTSEn RTSEn Out2
[15] CTSEn – CTS hardware flow control enable.
1: CTS hardware flow control is enable. Data is only transmitted when the UART0CTS
signal is asserted.
[14] RTSEn – RTS hardware flow control enable
1: RTS hardware flow control is enable. Data is only requested when there is space in
the receive FIFO for it to be received.
[13] Out2
This bit is the complement of the UART Out2 (nUARTOut2) modem status output.
That is, when the bit is programmed to 1, the output is 0.
For DTE this can be used as "Ring Indicator" (RI).
[12] Out1
This bit is the complement of the UART Out1 (nUARTOut1) modem status output.
That is, when the bit is programmed to 1 the output is 0.
For DTE this can be used as "Data Carrier Detect"(DCD).
[11] RTS – Request to send
This bit is the complement of the UART request to send, UART0RTS, modem status
output.
That is, when the bit is programmed to 1 then UART0RTS is LOW.
[10] DTS – Data transmit ready
This bit is the complement of the UART data transmit ready, UART0DTR, modem
status output.
That is, when the bit is programmed to 1 then UART0DTR is LOW.
[9] RXE – Receive enable
If this bit is set to 1, the receive section of the UART is enabled.
Data reception occurs for either UART signals or SIR signals depending on the setting
of the SIREN bit. When the UART is disabled in the middle of reception, it completes
the current character before stopping.
W7500 Datasheet Version1.0.0
28 27 26 25
res res res res
12 11 10 9
Out1 RTS DTR RXE
24 23 22 21
res res res res
8 7 6 5
res
TXE
20 19 18 17
res res res res
4 3 2 1
SIRLP SIREN
454 / 512
16
res
0
UARTEN