Register Map; Table 26 Pwm Channel 5 Register Map And Reset Values - Wiznet W7500 Reference Manual

18.15

Register map

The following Table 26 summarizes the PWM Channel-5 registers.
Offset Register
PWMCH5IR
0x00
reset value
PWMCH5IER
0x04
reset value
PWMCH5ICR
0x08
reset value
PWMCH5TCR
0x0C
reset value 0 0 0
PWMCH5PCR
0x10
reset value
PWMCH5PR
0x14
reset value
PWMCH5MR
0x18
0 0 0
reset value
PWMCH5LR
0x1C
1 1 1
reset value
PWMCH5UDMR
0x20
reset value
PWMCH5TCMR
0x24
reset value
PWMCH5PEEER
0x28
reset value
PWMCH5CMR
0x2C
reset value
PWMCH5CR
0x30
0 0 0
reset value
PWMCH5PDMR
0x34
reset value
PWMCH5DZER
0x38
reset value
PWMCH5DZCR
0x3C
reset value
W7500 Datasheet Version1.0.0

Table 26 PWM channel 5 register map and reset values

0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0
TCR
0 0 0 0 0 0 0 0 0 0 0
MR
0 0 0 0 0 0 0 0 0 0 0
LR
1 1 1 1 1 1 1 1 1 1 1
CR
0 0 0 0 0 0 0 0 0 0 0
DZC
0 0 0 0
비고
Channel-5 interrupt register
0 0 0
Channel-5 interrupt enable register
0 0 0
Channel-5 interrupt clear register
Write only register
Channel-5 Timer/Counter Register
0 0 0 0 0 0
Channel-5 Prescale Counter
PCR
Register
0 0 0 0 0 0
PR
Channel-5 Prescale Register
0 0 0 0 0 0
Channel-5 Match Register
0 0 0 0 0 0
Channel-5 Limit Register
1 1 1 1 1 1
Channel-5 Up-Down Mode Register
0
Channel-5 Timer/Counter Mode
TCM
Register
0 0
Channel-5 PWM output Enable and
PEEE
External input Enable Register
0 0
Channel-5 Capture Mode Register
0
Channel-5 Capture Register
0 0 0 0 0 0
Channel-5 Periodic Mode Register
0
Channel-5 Dead Zone Enable
Register
0
Channel-5 Dead Zone Counter
Register
0 0 0 0 0 0
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