Register Map; Table 42 Ssp0 Register Map And Reset Values - Wiznet W7500 Reference Manual

23.5

Register map

The following Table 42 summarizes the SSP0 registers.
Offset Register
SSPCR0
0x00
reset value
SSPCR1
0x04
reset value
SSPDR
0x08
reset value
SSPSR
0x0C
reset value
SSPCPSR
0x10
reset value
SSPIMSC
0x14
reset value
SSPRIS
0x18
reset value
SSPMIS
0x1C
reset value
SSPICR
0x20
reset value
SSPDMACR
0x24
reset value
W7500 Datasheet Version1.0.0

Table 42 SSP0 register map and reset values

0 0
x x
0 0 0 0 0 0 0 0 0 0 0
0
Data
x x x x x x x x x x x
0 0
CPSDVSR
0 0 0 0 0
0
1
0
비고
Control register 0
0 0 0
Control register 1
0 0 0
Data register
x x x
Status register
0 1 1
Clock prescale register
0 0 0
Interrupt Mask set or clear register
0 0 0
Raw interrupt status register
0 0 0
Masked interrupt status register
0 0 0
Interrupt clear register
0 0
DMA control regsiter
0 0
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