Inter-Integrated Circuit Interface (I2C); Introduction; Features; Functional Description - Wiznet W7500 Reference Manual

21

Inter-integrated circuit interface (I2C)

21.1

Introduction

2
The �� (inter-integrated circuit) bus interface handles communications between the
microcontroller and the serial ��
Mode(400Kbps).
21.2

Features

•
Use APB interface
•
Supports Slave and Master Mode
•
Standard mode (up to 100 KHz)
•
Fast mode (up to 400 KHz)
•
Supports 7 bit Slave address mode
•
Start/Stop/Repeated Start detection
•
Start/Stop/Repeated Start/Acknowledge generation
•
Control the Read/Write operation
•
General Call enable or disable
•
Slave busy detection
•
Repeated START
21.3

Functional description

2
�� is comprised of both master and slave functions. For proper operation, the SDA and SCL
pins must be configured as open-drain signals. A ��
SCL
SDA
Figure 46 shows the I2C block diagram.
In addition to receiving and transmitting data, this interface converts it from serial to
parallel format and vice versa. The interrupt is enabled or disabled by software. The
W7500 Datasheet Version1.0.0
2
bus. It supports standard speed mode(100Kbps), Fast
R R
PUP PUP

Figure 45. I2C Bus Configuration

2
bus configuration is shown in Figure 45.
I C Bus
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