Figure 72 Motorola Spi Frame Format, Single Transfer, With Spo=1 And Sph=0 - Wiznet W7500 Reference Manual

• the nSSPOE pad enable signal is forced HIGH, making the transmit pad high impedance
• when the PrimeCell SSP is configured as a master, the nSSPCTLOE line is driven LOW,
enabling the SSPCLKOUT pad, active-LOW enable
• when the PrimeCell SSP is configured as a slave, the nSSPCTLOE line is driven HIGH,
disabling the SSPCLKOUT pad, active-LOW enable.
If the PrimeCell SSP is enabled and there is valid data within the transmit FIFO, the start of
transmission is signified by the SSPFSSOUT master signal being driven LOW. The nSSPOE line
is driven LOW, enabling the master SSPTXD output pad. After an additional one half
SSPCLKOUT period, both master and slave valid data is enabled onto their respective
transmission lines. At the same time, the SSPCLKOUT is enabled with a rising edge transition.
Data is then captured on the falling edges and propagated on the rising edges of the
SSPCLKOUT signal.
In the case of a single word transfer after all bits have been transferred, the SSPFSSOUT line
is returned to its idle HIGH state one SSPCLKOUT period after the last bit has been captured.
For continuous back-to-back transfers, the SSPFSSOUT pin is held LOW between successive
data words and termination is the same as that of the single word transfer.
Figure 72 shows a single transmission signal sequence for Motorola SPI format with SPO=1,
SPH=0.
SSPCLKOUT/
SSPCLKIN
SSPFSSOUT/
SSPFSSIN
SSPRXD
nSSPOE
SSPTXD

Figure 72 Motorola SPI frame format, single transfer, with SPO=1 and SPH=0

Figure 73 shows a continuous transmission signal sequence for Motorola SPI format with
SPO=1, SPH=0. In Figure 9, Q is an undefined signal.
W7500 Datasheet Version1.0.0
MSB
4 to 16 bits
MSB MSB
LSB LSB Q
LSB LSB
488 / 512