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18.17
Register map
The following Table 27 summarizes the PWM Channel-5 registers.
Offset
Register
PWMCH6IR
0x00
reset value
PWMCH6IER
0x04
reset value
PWMCH6ICR
0x08
reset value
PWMCH6TCR
0x0C
reset value
0
0
0
PWMCH6PCR
0x10
reset value
PWMCH6PR
0x14
reset value
PWMCH6MR
0x18
0
0
0
reset value
PWMCH6LR
0x1C
1
1
1
reset value
PWMCH6UDMR
0x20
reset value
PWMCH6TCMR
0x24
reset value
PWMCH6PEEER
0x28
reset value
PWMCH6CMR
0x2C
reset value
PWMCH6CR
0x30
0
0
0
reset value
PWMCH6PDMR
0x34
reset value
PWMCH6DZER
0x38
reset value
PWMCH6DZCR
0x3C
reset value
W7500 Datasheet Version1.0.0
Table 27 PWM channel 6 register map and reset values
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
TCR
0
0
0
0
0
0
0
0
0
0
0
MR
0
0
0
0
0
0
0
0
0
0
0
LR
1
1
1
1
1
1
1
1
1
1
1
CR
0
0
0
0
0
0
0
0
0
0
0
DZC
0
0
0
0
비고
Channel-6 interrupt register
0
0
0
Channel-6 interrupt enable register
0
0
0
Channel-6 interrupt clear register
Write only register
Channel-6 Timer/Counter Register
0
0
0
0
0
0
Channel-6 Prescale Counter
PCR
Register
0
0
0
0
0
0
PR
Channel-6 Prescale Register
0
0
0
0
0
0
Channel-6 Match Register
0
0
0
0
0
0
Channel-6 Limit Register
1
1
1
1
1
1
Channel-6 Up-Down Mode Register
0
Channel-6 Timer/Counter Mode
TCM
Register
0
0
Channel-6 PWM output Enable and
PEEE
External input Enable Register
0
0
Channel-6 Capture Mode Register
0
Channel-6 Capture Register
0
0
0
0
0
0
Channel-6 Periodic Mode Register
0
Channel-6 Dead Zone Enable
Register
0
Channel-6 Dead Zone Counter
Register
0
0
0
0
0
0
364 / 512
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