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16.5
Register map
The following Table 19 summarizes the DMA registers.
Offset
Register
DMA_STATUS
0x000
reset value
DMA_CFG
0x004
reset value
DMA_CTRL_BASE_PTR
0x008
reset value
DMA_ALT_CTRL_BASE_PTR
0x00C
reset value
DMA_WAITONREQ_STATUS
0x010
reset value
DMA_CHNL_SW_REQUEST
0x014
reset value
DMA_CHNL_USEBURST_SET
0x018
reset value
DMA_CHNL_USEBURST_CLR
0x01C
reset value
DMA_CHNL_REQ_MASK_SET
0x020
reset value
DMA_CHNL_REQ_MASK_CLR
0x024
reset value
DMA_CHNL_ENABLE_SET
0x028
reset value
DMA_CHNL_ENABLE_CLR
0x02C
reset value
DMA_CHNL_PRI_ALT_SET
0x030
reset value
DMA_CHNL_PRI_ALT_CLR
0x034
reset value
DMA_CHNL_PRIORITY_SET
0x038
reset value
DMA_CHNL_PRIORITY_CLR
0x03C
reset value
DMA_ERR_CLR
0x04C
reset value
W7500 Datasheet Version1.0.0
Table 19 DMA register map and reset values
CTRL_BASE_PTR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ALT_CTRL_BASE_PTR
0
0
0
0
0
0
0
0
0
0
STATE
0
0
0
0
PROT_CTRL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMA_WAITONREQ
0
0
0
0
CHNL_SW_REQUEST
CHNL_USEBURST_SET
0
0
0
0
CHNL_USEBURST_CLR
CHNL_REQ_MASK_SET
0
0
0
0
CHNL_REQ_MASK_CLR
CHNL_ENABLE_SET
0
0
0
0
CHNL_ENABLE_CLR
CHNL_PRI_ALT_SET
0
0
0
0
CHNL_PRI_ALT_CLR
CHNL_PRIORITY_SET
0
0
0
0
CHNL_PRIORITY_CLR
282 / 512
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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