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18.11
Register map
The following Table 24 summarizes the PWM Channel-3 registers.
Offset
Register
PWMCH3IR
0x00
reset value
PWMCH3IER
0x04
reset value
PWMCH3ICR
0x08
reset value
PWMCH3TCR
0x0C
reset value
0
0
0
PWMCH3PCR
0x10
reset value
PWMCH3PR
0x14
reset value
PWMCH3MR
0x18
0
0
0
reset value
PWMCH3LR
0x1C
1
1
1
reset value
PWMCH3UDMR
0x20
reset value
PWMCH3TCMR
0x24
reset value
PWMCH3PEEER
0x28
reset value
PWMCH3CMR
0x2C
reset value
PWMCH3CR
0x30
0
0
0
reset value
PWMCH3PDMR
0x34
reset value
PWMCH3DZER
0x38
reset value
PWMCH3DZCR
0x3C
reset value
W7500 Datasheet Version1.0.0
Table 24 PWM channel 3 register map and reset values
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
TCR
0
0
0
0
0
0
0
0
0
0
0
MR
0
0
0
0
0
0
0
0
0
0
0
LR
1
1
1
1
1
1
1
1
1
1
1
CR
0
0
0
0
0
0
0
0
0
0
0
DZC
0
0
0
0
비고
Channel-3 interrupt register
0
0
0
Channel-3 interrupt enable register
0
0
0
Channel-3 interrupt clear register
Write only register
Channel-3 Timer/Counter Register
0
0
0
0
0
0
Channel-3 Prescale Counter
PCR
Register
0
0
0
0
0
0
PR
Channel-3 Prescale Register
0
0
0
0
0
0
Channel-3 Match Register
0
0
0
0
0
0
Channel-3 Limit Register
1
1
1
1
1
1
Channel-3 Up-Down Mode Register
0
Channel-3 Timer/Counter Mode
TCM
Register
0
0
Channel-3 PWM output Enable and
PEEE
External input Enable Register
0
0
Channel-3 Capture Mode Register
0
Channel-3 Capture Register
0
0
0
0
0
0
Channel-3 Periodic Mode Register
0
Channel-3 Dead Zone Enable
Register
0
Channel-3 Dead Zone Counter
Register
0
0
0
0
0
0
337 / 512
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