Functional Description; Clock Prescaler; Transmit Fifo; Figure 65. Ssp Block Diagram - Wiznet W7500 Reference Manual

23.3

Functional description

Figure 65 shows the SSP block diagram.
APB
Bus
Interface
Register
block
DMA
signals
DMA
interface
23.3.1

Clock prescaler

When configured as a master, an internal prescaler is used to provide the serial output clock.
The prescaler may be programmed through the SSPCPSR register to divide the SSPCLK by a
factor of 2 to 254 in two steps. As the least significant bit of the SSPCPSR register is not used,
division by an odd number is impossible and this ensures a symmetrical (equal mark space
ratio) clock is generated.
The output of this prescaler is further divided by a factor 1 to 256 through the programming
of the SSPCR0 control register, to give a final master output clock.
23.3.2

Transmit FIFO

The common transmit FIFO is a 16-bit wide, 8-locations deep, First-In, First-Out (FIFO)
memory buffer. CPU data written across the AMBA APB interface are stored in the buffer
until it is read out by the transmit logic.
When configured as a master or a slave, parallel data is written into the transmit FIFO prior
to serial conversion and is transmitted to the attached slave or master through the SSPTXD
pin.
W7500 Datasheet Version1.0.0
TxFIFO
RxFIFO
SSPCLK
Clock
Prescale
Prescaler
value

Figure 65. SSP block diagram

FIFO Status
and
Interrupt
Generation
Transmit
SSPCLKDIV
and
Receive
logic
SSPTXINTR
SSPINTR
SSPRXINTR
SSPTXD
SSPCLKOUT
SSPCLKIN
SSPRXD
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