Motorola Spi Frame Format; Figure 68. Texas Instruments Synchronous Serial Frame Format, Continuous Transfers - Wiznet W7500 Reference Manual

from the serial shifter to the receive FIFO on the first rising edge of PCLK after the LSB has
been latched.
Figure 68 shows the Texas Instruments synchronous serial frame format when back-to-back
frames are transmitted.
SSPCLKOUT/
SSPCLKIN
SSPFSSOUT/
SSPFSSIN
SSPTXD/
MSB LSB
SSPRXD
4 to 16 bits
nSSPOE (=0)
Figure 68.
Texas Instruments synchronous serial frame format, continuous transfers
23.3.14

Motorola SPI frame format

The Motorola SPI interface is a four-wire interface where the SSPFSSOUT signal behaves as a
slave select. The main feature of the Motorola SPI format is that you can program the
inactive state and phase of the SSPCLKOUT signal using the SPO and SPH bits of the SSPSCR0
control register.
SPO, clock polarity
When the SPO clock polarity control bit is LOW, it produces a steady state LOW value on the
SSPCLKOUT pin. If the SPO clock polarity control bit is HIGH, a steady state HIGH value is
placed on the SSPCLKOUT pin when data is not being transferred.
SPH, clock phase
The SPH control bit selects the clock edge that captures data and enables it to change state.
It has the most impact on the first bit transmitted by either permitting or not permitting a
clock transition before the first data capture edge.
When the SPH phase control bit is LOW, data is captured on the first clock edge transition.
When the SPH clock phase control bit is HIGH, data is captured on the second clock edge
transition.
Figure 69 and Figure 70 show single and continuous transmission signal sequences for
Motorola SPI format with SPO=0, SPH=0.
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W7500 Datasheet Version1.0.0