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WIZnet W7500 Manuals
Manuals and User Guides for WIZnet W7500. We have
3
WIZnet W7500 manuals available for free PDF download: Reference Manual, Information
WIZnet W7500 Reference Manual (512 pages)
Internet Offload Processor
Brand:
WIZnet
| Category:
Computer Hardware
| Size: 10.71 MB
Table of Contents
Table of Contents
2
1 Documentation Conventions
29
List of Abbreviations
29
Glossary
29
Register Bit Conventions
31
2 System and Memory Overview
32
System Architecture
32
Figure 1 W7500 System Architecture
32
Memory Organization
33
2.2.1 Introduction
33
2.2.2 Memory Map
34
Figure 2 W7500 Memory Map
34
3 System Configuration Controller (SYSCFG)
35
Introduction
35
Registers (Base Address : 0X4001_F000)
35
3.2.1 REMAP Register
35
3.2.2 RESETOP Register
35
3.2.3 RSTINFO Register
36
4 Interrupt and Events
36
Introduction
36
Interrupt Assignments
37
Table 1 W7500 Interrupt Assignments
37
Event
38
5 Power Supply
38
Introduction
38
Voltage Regulator
38
Power Supply Supervisor
38
Figure 3 por Reset Waveform
38
Low-Power Modes
39
5.4.1 Sleep Mode
39
5.4.2 Peripheral Clock Gating
39
Table 2 W7500 Sleep Mode Summary
39
6 System Tick Timer
40
Introduction
40
Features
40
Functional Description
40
Registers (Base : 0Xe000_E000)
41
System Timer Control and Status Register (SYST_CSR)
41
Systick Reload Value Register (SYST_RVR)
41
Systick Current Value Register (SYST_CVR)
42
Systick Calibration Value Register (SYST_CALIB)
42
7 Tcpipcore Offload Engine (TOE)
43
Introduction
43
Features
43
Functional Description
43
Figure 4 TOE Block Diagram
43
TOE Memory Map
44
Figure 5. Register & Memory Organization
45
Common Register Map
46
Socket Register Map
46
Table 3. Offset Address for Common Register
46
Memory
47
Table 4. Offset Address in Socket N Register Block
47
Common Register (Base : 0X4100_0000)
49
VERSIONR (TOE Version Register)
49
TCKCNTR (Ticker Counter Register)
49
IR (Interrupt Register)
49
IMR (Interrupt Mask Register)
50
IRCR (Interrupt Clear Register)
51
SIR (Socket Interrupt Register)
51
MD (Mode Register)
52
SIMR (Socket Interrupt Mask Register)
52
PTIMER (PPP Link Control Protocol Request Timer Register)
53
PHAR (Destination Hardware Address Register in Pppoe)
54
PMAGICR (PPP Link Control Protocol Magic Number Register)
54
PMRUR (Maximum Receive Unit Register in Pppoe)
55
PSIDR (Session ID Register in Pppoe)
55
SHAR (Source Hardware Address Register)
56
GAR (Gateway Address)
57
SUBR ( Subnet Mask Register)
57
NCONFLR ( Network Configuration Lock Register)
58
SIPR (Source IP Address Register)
58
RCR (Retry Counter Register)
59
RTR (Retry Time Register)
59
UIPR (Unreachable IP Address Register)
61
UPORTR (Unreachable Port Register)
62
Socket Register (Base : 0X4101_0000 + 0X0004_000 X N)[N=0
62
Sn_Mr (Socket N Mode Register)
62
Sn_Cr (Socket N Command Register)
64
Sn_Ir (Socket N Interrupt Register)
67
Sn_Imr (Socket N Interrupt Mask Register)
67
Sn_Icr (Socket N Interrupt Clear Register)
68
Sn_Sr (Socket N Status Register)
69
Sn_Pnr (Socket N Protocol Number Register)
71
Sn_Tosr (Socket N IP Type of Service Register)
71
Sn_Fragr (Socket N Fragment Offset Register)
72
Sn_Ttlr (Socket N TTL Register)
72
Sn_Mssr (Socket N Maximum Segment Register)
73
Sn_Portr (Socket N Source Port Register)
73
Sn_Dhar (Socket N Destination Hardware Address Register)
74
Sn_Dipr (Socket N Destination IP Address Register)
75
Sn_Dportr (Socket N Destination Port Number Register)
75
Sn_Katmr (Socket N Keep Alive Timer Register)
76
Sn_Rcr (Socket N Retry Counter Register)
77
Sn_Rtr (Socket N Retry Time Register)
77
Sn_Txbuf_Size (Socket N TX Buffer Size Register)
78
Sn_Tx_Fsr (Socket N TX Free Size Register)
79
Sn_Tx_Rd (Socket N TX Read Pointer Register)
80
Sn_Tx_Wr (Socket N TX Write Pointer Register)
80
Sn_Rxbuf_Size (Socket N RX Buffer Size Register)
81
Sn_Rx_Rd (Socket N RX Read Pointer Register)
82
Sn_Rx_Rsr (Socket N RX Received Size Register)
82
Sn_Rx_Wr (Socket N RX Write Pointer Register)
83
8 Booting Sequence
84
Table 5 Operation of Mode Selection
84
Figure 6. Operation of Boot Code
84
9 Embedded Flash Memory
85
Flash Main Features
85
Flash Memory Functional Description
85
Flash Memory Organization
85
Table 6 Description of Flash Memory
85
Read Operations
87
Figure 7. Flash Reading Sequence
88
Flash Erase Operations
88
Figure 8. Flash Erase Operations
89
Figure 9. Main Flash Memory Programming Sequence
90
Flash Program Operation
90
Memory Protection
91
Read Protection
91
Write Protection
91
10 Clock Reset Generator (CRG)
92
Introduction
92
Features
92
10.2.1 Reset
92
Clock
92
Functional Description
93
10.3.1 External Oscillator Clock
93
Table 7 External Oscillator Clock Sources
93
Figure 10 CRG Block Diagram
93
10.3.2 RC Oscillator Clock
94
10.3.3 Pll
94
10.3.4 Generated Clock
94
Registers (Base Address : 0X4100_1000)
95
OSC Power down Register (OSC_PDR)
95
PLL Power down Register (PLL_PDR)
95
PLL Frequency Calculating Register (PLL_FCR)
95
PLL Output Enable Register (PLL_OER)
96
PLL Bypass Register (PLL_BPR)
96
PLL Input Clock Source Select Register (PLL_IFSR)
97
FCLK Source Select Register (FCLK_SSR)
97
FCLK Prescale Value Select Register (FCLK_PVSR)
98
SSPCLK Source Select Register (SSPCLK_SSR)
98
SSPCLK Prescale Value Select Register (SSPCLK_PVSR)
99
ADCCLK Source Select Register (ADCCLK_SSR)
99
ADCCLK Prescale Value Select Register (ADCCLK_PVSR)
100
TIMER0CLK Source Select Register (TIMER0CLK_SSR)
100
TIMER0CLK Prescale Value Select Register (TIMER0CLK_PVSR)
100
TIMER1CLK Source Select Register (TIMER1CLK_SSR)
101
TIMER1CLK Prescale Value Select Register (TIMER1CLK_PVSR)
101
PWM0CLK Source Select Register (PWM0CLK_SSR)
102
PWM0CLK Prescale Value Select Register (PWM0CLK_PVSR)
103
PWM1CLK Source Select Register (PWM1CLK_SSR)
103
PWM1CLK Prescale Value Select Register (PWM1CLK_PVSR)
104
PWM2CLK Source Select Register (PWM2CLK_SSR)
104
PWM2CLK Prescale Value Select Register (PWM2CLK_PVSR)
105
PWM3CLK Source Select Register (PWM3CLK_SSR)
105
PWM3CLK Prescale Value Select Register (PWM3CLK_PVSR)
106
PWM4CLK Source Select Register (PWM4CLK_SSR)
106
PWM4CLK Prescale Value Select Register (PWM4CLK_PVSR)
107
PWM5CLK Source Select Register (PWM5CLK_SSR)
107
PWM5CLK Prescale Value Select Register (PWM5CLK_PVSR)
108
PWM6CLK Source Select Register (PWM6CLK_SSR)
108
PWM6CLK Prescale Value Select Register (PWM6CLK_PVSR)
109
PWM7CLK Source Select Register (PWM7CLK_SSR)
109
PWM7CLK Prescale Value Select Register (PWM7CLK_PVSR)
110
WDOGCLK High Speed Source Select Register (WDOGCLK_HS_SSR)
110
WDOGCLK High Speed Prescale Value Select Register (WDOGCLK_HS_PVSR)
111
UARTCLK Source Select Register (UARTCLK_SSR)
111
UARTCLK Prescale Value Select Register (UARTCLK_PVSR)
112
MIICLK Enable Control Register (MIICLK_ECR)
112
Monitoring Clock Source Select Register (MONCLK_SSR)
113
Register Map
115
Table 8 CRG Register Map and Reset Values
115
11 Random Number Generator (RNG)
117
Introduction
117
Features
117
Functional Description
117
Figure 11. Random Number Generator Block Diagram
117
Operation RNG
118
Figure 12. Flow Chart of RNG Operation
118
Registers (Base Address : 0X4000_7000)
119
RNG Clock Select Register (RNG_CLKSEL)
119
RNG Run Register (RNG_RUN)
119
RNG SEED Register (RNG_SEED)
119
RNG Manual Mode Select Register (RNG_MODE)
120
RNG Random Number Value Register (RNG_RN)
120
RNG Polynomial Register (RNG_POLY)
121
Register Map
122
Table 9 RNG Register Map and Reset Values
122
12 Alternate Function Controller (AFC)
123
Introduction
123
Features
123
Functional Description
123
Table 10 Functional Description Table
123
Registers (Base Address : 0X4100_2000)
125
PA_00 Pad Alternate Function Select Register (PA_00_AFR)
125
PA_01 Pad Alternate Function Select Register (PA_01_AFR)
125
PA_02 Pad Alternate Function Select Register (PA_02_AFR)
126
PA_03 Pad Alternate Function Select Register (PA_03_AFR)
126
PA_04 Pad Alternate Function Select Register (PA_04_AFR)
127
PA_05 Pad Alternate Function Select Register (PA_05_AFR)
127
PA_06 Pad Alternate Function Select Register (PA_06_AFR)
128
PA_07 Pad Alternate Function Select Register (PA_07_AFR)
128
PA_08 Pad Alternate Function Select Register (PA_08_AFR)
129
PA_09 Pad Alternate Function Select Register (PA_09_AFR)
129
PA_10 Pad Alternate Function Select Register (PA_10_AFR)
130
PA_11 Pad Alternate Function Select Register (PA_11_AFR)
130
PA_12 Pad Alternate Function Select Register (PA_12_AFR)
131
PA_13 Pad Alternate Function Select Register (PA_13_AFR)
131
PA_14 Pad Alternate Function Select Register (PA_14_AFR)
132
PA_15 Pad Alternate Function Select Register (PA_15_AFR)
132
PB_00 Pad Alternate Function Select Register (PB_00_AFR)
133
PB_01 Pad Alternate Function Select Register (PB_01_AFR)
133
PB_02 Pad Alternate Function Select Register (PB_02_AFR)
134
PB_03 Pad Alternate Function Select Register (PB_03_AFR)
134
PB_04 Pad Alternate Function Select Register (PB_04_AFR)
135
PB_05 Pad Alternate Function Select Register (PB_05_AFR)
135
PB_06 Pad Alternate Function Select Register (PB_06_AFR)
136
PB_07 Pad Alternate Function Select Register (PB_07_AFR)
136
PB_08 Pad Alternate Function Select Register (PB_08_AFR)
137
PB_09 Pad Alternate Function Select Register (PB_09_AFR)
137
PB_10 Pad Alternate Function Select Register (PB_10_AFR)
138
PB_11 Pad Alternate Function Select Register (PB_11_AFR)
138
PB_12 Pad Alternate Function Select Register (PB_12_AFR)
139
PB_13 Pad Alternate Function Select Register (PB_13_AFR)
139
PB_14 Pad Alternate Function Select Register (PB_14_AFR)
140
PB_15 Pad Alternate Function Select Register (PB_15_AFR)
140
PC_00 Pad Alternate Function Select Register (PC_00_AFR)
141
PC_01 Pad Alternate Function Select Register (PC_01_AFR)
141
PC_02 Pad Alternate Function Select Register (PC_02_AFR)
142
PC_03 Pad Alternate Function Select Register (PC_03_AFR)
142
PC_04 Pad Alternate Function Select Register (PC_04_AFR)
143
PC_05 Pad Alternate Function Select Register (PC_05_AFR)
143
PC_06 Pad Alternate Function Select Register (PC_06_AFR)
144
PC_07 Pad Alternate Function Select Register (PC_07_AFR)
144
PC_08 Pad Alternate Function Select Register (PC_08_AFR)
145
PC_09 Pad Alternate Function Select Register (PC_09_AFR)
145
PC_10 Pad Alternate Function Select Register (PC_10_AFR)
146
PC_11 Pad Alternate Function Select Register (PC_11_AFR)
146
PC_12 Pad Alternate Function Select Register (PC_12_AFR)
147
PC_13 Pad Alternate Function Select Register (PC_13_AFR)
147
PC_14 Pad Alternate Function Select Register (PC_14_AFR)
148
PC_15 Pad Alternate Function Select Register (PC_15_AFR)
148
PD_00 Pad Alternate Function Select Register (PD_00_AFR)
149
PD_01 Pad Alternate Function Select Register (PD_01_AFR)
149
PD_02 Pad Alternate Function Select Register (PD_02_AFR)
150
PD_03 Pad Alternate Function Select Register (PD_03_AFR)
150
PD_04 Pad Alternate Function Select Register (PD_04_AFR)
151
Register Map
152
Table 11 AFC Register Map and Reset Values
152
13 External Interrupt (EXTI)
155
Introduction
155
Features
155
Functional Description
155
Figure 13. External Interrupt Diagram
156
Registers (Base Address : 0X4100_2000)
157
PA_00 External Interrupt Enable Register (PA_00_EXTINT)
157
PA_01 External Interrupt Enable Register (PA_01_EXTINT)
157
PA_02 External Interrupt Enable Register (PA_02_EXTINT)
158
PA_03 External Interrupt Enable Register (PA_03_EXTINT)
158
PA_04 External Interrupt Enable Register (PA_04_EXTINT)
159
PA_05 External Interrupt Enable Register (PA_05_EXTINT)
159
PA_06 External Interrupt Enable Register (PA_06_EXTINT)
160
PA_07 External Interrupt Enable Register (PA_07_EXTINT)
160
PA_08 External Interrupt Enable Register (PA_08_EXTINT)
161
PA_09 External Interrupt Enable Register (PA_09_EXTINT)
162
PA_10 External Interrupt Enable Register (PA_10_EXTINT)
162
PA_11 External Interrupt Enable Register (PA_11_EXTINT)
163
PA_12 External Interrupt Enable Register (PA_12_EXTINT)
163
PA_13 External Interrupt Enable Register (PA_13_EXTINT)
164
PA_14 External Interrupt Enable Register (PA_14_EXTINT)
164
PA_15 External Interrupt Enable Register (PA_15_EXTINT)
165
PB_00 External Interrupt Enable Register (PB_00_EXTINT)
165
PB_01 External Interrupt Enable Register (PB_01_EXTINT)
166
PB_02 External Interrupt Enable Register (PB_02_EXTINT)
166
PB_03 External Interrupt Enable Register (PB_03_EXTINT)
167
PB_04 External Interrupt Enable Register (PB_04_EXTINT)
168
PB_05 External Interrupt Enable Register (PB_05_EXTINT)
168
PB_06 External Interrupt Enable Register (PB_06_EXTINT)
169
PB_07 External Interrupt Enable Register (PB_07_EXTINT)
169
PB_08 External Interrupt Enable Register (PB_08_EXTINT)
170
PB_09 External Interrupt Enable Register (PB_09_EXTINT)
170
PB_10 External Interrupt Enable Register (PB_10_EXTINT)
171
PB_11 External Interrupt Enable Register (PB_11_EXTINT)
171
PB_12 External Interrupt Enable Register (PB_12_EXTINT)
172
PB_13 External Interrupt Enable Register (PB_13_EXTINT)
172
PB_14 External Interrupt Enable Register (PB_14_EXTINT)
173
PB_15 External Interrupt Enable Register (PB_15_EXTINT)
174
PC_00 External Interrupt Enable Register (PC_00_EXTINT)
174
PC_01 External Interrupt Enable Register (PC_01_EXTINT)
175
PC_02 External Interrupt Enable Register (PC_02_EXTINT)
175
PC_03 External Interrupt Enable Register (PC_03_EXTINT)
176
PC_04 External Interrupt Enable Register (PC_04_EXTINT)
176
PC_05 External Interrupt Enable Register (PC_05_EXTINT)
177
PC_06 External Interrupt Enable Register (PC_06_EXTINT)
177
PC_07 External Interrupt Enable Register (PC_07_EXTINT)
178
PC_08 External Interrupt Enable Register (PC_08_EXTINT)
178
PC_09 External Interrupt Enable Register (PC_09_EXTINT)
179
PC_10 External Interrupt Enable Register (PC_10_EXTINT)
180
PC_11 External Interrupt Enable Register (PC_11_EXTINT)
180
PC_12 External Interrupt Enable Register (PC_12_EXTINT)
181
PC_13 External Interrupt Enable Register (PC_13_EXTINT)
181
PC_14 External Interrupt Enable Register (PC_14_EXTINT)
182
PC_15 External Interrupt Enable Register (PC_15_EXTINT)
182
PD_00 External Interrupt Enable Register (PD_00_EXTINT)
183
PD_01 External Interrupt Enable Register (PD_01_EXTINT)
183
PD_02 External Interrupt Enable Register (PD_02_EXTINT)
184
PD_03 External Interrupt Enable Register (PD_03_EXTINT)
184
PD_04 External Interrupt Enable Register (PD_04_EXTINT)
185
Register Map
186
Table 12 EXTINT Register Map and Reset Values
186
14 Pad Controller (PADCON)
189
Introduction
189
Features
189
Functional Description
189
Figure 14. Function Schematic of Digital I/O Pad
189
Registers (Base Address : 0X4100_3000)
190
14.4.1 PA_00 Pad Control Register
190
Figure 15. Function Schematic of Digital/Analog Mux IO Pad
190
14.4.2 PA_01 Pad Control Register
191
14.4.3 PA_02 Pad Control Register
192
14.4.4 PA_03 Pad Control Register
192
14.4.5 PA_04 Pad Control Register
193
14.4.6 PA_05 Pad Control Register
194
14.4.7 PA_06 Pad Control Register
194
14.4.8 PA_07 Pad Control Register
195
14.4.9 PA_08 Pad Control Register
196
PA_09 Pad Control Register
196
PA_10 Pad Control Register
197
PA_11 Pad Control Register
198
PA_12 Pad Control Register
199
PA_13 Pad Control Register
199
PA_14 Pad Control Register
200
PA_15 Pad Control Register
201
PB_00 Pad Control Register
201
PB_01 Pad Control Register
202
PB_02 Pad Control Register
203
PB_03 Pad Control Register
203
PB_04 Pad Control Register
204
PB_05 Pad Control Register
205
PB_06 Pad Control Register
205
PB_07 Pad Control Register
206
PB_08 Pad Control Register
207
PB_09 Pad Control Register
208
PB_10 Pad Control Register
208
PB_11 Pad Control Register
209
PB_12 Pad Control Register
210
PB_13 Pad Control Register
210
PB_14 Pad Control Register
211
PB_15 Pad Control Register
212
PC_00 Pad Control Register
212
PC_01 Pad Control Register
213
PC_02 Pad Control Register
214
PC_03 Pad Control Register
214
PC_04 Pad Control Register
215
PC_05 Pad Control Register
216
PC_06 Pad Control Register
216
PC_07 Pad Control Register
217
PC_08 Pad Control Register
218
PC_09 Pad Control Register
219
PC_10 Pad Control Register
219
PC_11 Pad Control Register
220
PC_12 Pad Control Register
221
PC_13 Pad Control Register
221
PC_14 Pad Control Register
222
PC_15 Pad Control Register
223
PD_00 Pad Control Register
223
PD_01 Pad Control Register
224
PD_02 Pad Control Register
225
PD_03 Pad Control Register
225
PD_04 Pad Control Register
226
Register Map
228
Table 13 PAD Controller Register Map and Reset Values
228
15 General-Purpose I/Os(GPIO)
232
Introduction
232
Features
232
Functional Description
232
Figure 16. GPIO Block Diagram
232
Figure 17. GPIO Flow Chart
233
Masked Access
233
Figure 18. MASK LOWBYTE Access
234
Figure 19 MASK HIGHBYTE Access
234
GPIOA Registers(Address Base: 0X4200_0000)
235
GPIOA Data Register(GPIOA_DATA)
235
GPIOA Enable Set Register(GPIOA_OUTENSET)
235
GPIOA Output Latch Register(GPIOA_DATAOUT)
235
GPIOA Enable Clear Register(GPIOA_OUTENCLR)
236
GPIOA Interrupt Enable Set Register(GPIOA_ INTENSET)
236
GPIOA Interrupt Enable Clear Register(GPIOA_ INTENCLR)
237
GPIOA Interrupt Type Set Register(GPIOA_ INTTYPESET)
237
GPIOA Interrupt Polarity Set Register(GPIOA_ INTPOLSET)
238
GPIOA Interrupt Type Clear Register(GPIOA_ INTTYPECLR)
238
GPIOA Interrupt Polarity Clear Register(GPIOA_ INTPOLCLR)
239
GPIOA Interrupt Status/Interrupt Clear Register
239
Intclear)
239
GPIOA Lower Byte Masked Access Register(GPIOA_ LB_MASKED)
240
GPIOA Upper Byte Masked Access Register(GPIOA_ UB_MASKED)
240
Register Map
242
Table 14 GPIOA Register Map and Reset Values
242
GPIOB Data Register(GPIOB_DATA)
243
GPIOB Enable Set Register(GPIOB_OUTENSET)
243
GPIOB Output Latch Register(GPIOB_DATAOUT)
243
GPIOB Registers(Address Base: 0X4300_0000)
243
GPIOB Enable Clear Register(GPIOB_OUTENCLR)
244
GPIOB Interrupt Enable Set Register(GPIOB_ INTENSET)
244
GPIOB Interrupt Enable Clear Register(GPIOB_ INTENCLR)
245
GPIOB Interrupt Type Set Register(GPIOB_ INTTYPESET)
245
GPIOB Interrupt Polarity Set Register(GPIOB_ INTPOLSET)
246
GPIOB Interrupt Type Clear Register(GPIOB_ INTTYPECLR)
246
GPIOB Interrupt Polarity Clear Register(GPIOB_ INTPOLCLR)
247
GPIOB Interrupt Status/Interrupt Clear Register
248
Intclear)
248
GPIOB Lower Byte Masked Access Register(GPIOB_ LB_MASKED)
248
GPIOB Upper Byte Masked Access Register(GPIOB_ UB_MASKED)
248
Register Map
250
Table 15 GPIOB Register Map and Reset Values
250
GPIOC Registers(Address Base: 0X4400_0000)
251
GPIOC Data Register(GPIOC_DATA)
251
GPIOC Enable Set Register(GPIOC_OUTENSET)
251
GPIOC Output Latch Register(GPIOC_DATAOUT)
251
GPIOC Enable Clear Register(GPIOC_OUTENCLR)
252
GPIOC Interrupt Enable Set Register(GPIOC_ INTENSET)
252
GPIOC Interrupt Enable Clear Register(GPIOC_ INTENCLR)
253
GPIOC Interrupt Type Set Register(GPIOC_ INTTYPESET)
253
GPIOC Interrupt Polarity Set Register(GPIOC_ INTPOLSET)
254
GPIOC Interrupt Type Clear Register(GPIOC_ INTTYPECLR)
254
GPIOC Interrupt Polarity Clear Register(GPIOC_ INTPOLCLR)
255
GPIOC Interrupt Status/Interrupt Clear Register
256
Intclear)
256
GPIOC Lower Byte Masked Access Register(GPIOC_ LB_MASKED)
256
GPIOC Upper Byte Masked Access Register(GPIOC_ UB_MASKED)
257
Register Map
258
Table 16 GPIOC Register Map and Reset Values
258
GPIOD Data Register(GPIOD_DATA)
259
GPIOD Enable Set Register(GPIOD_OUTENSET)
259
GPIOD Output Latch Register(GPIOD_DATAOUT)
259
GPIOD Registers(Address Base: 0X4500_0000)
259
GPIOD Enable Clear Register(GPIOD_OUTENCLR)
260
GPIOD Interrupt Enable Set Register(GPIOD_ INTENSET)
260
GPIOD Interrupt Enable Clear Register(GPIOD_ INTENCLR)
261
GPIOD Interrupt Type Set Register(GPIOD_ INTTYPESET)
261
GPIOD Interrupt Polarity Set Register(GPIOD_ INTPOLSET)
262
GPIOD Interrupt Type Clear Register(GPIOD_ INTTYPECLR)
262
GPIOD Interrupt Polarity Clear Register(GPIOD_ INTPOLCLR)
263
GPIOD Interrupt Status/Interrupt Clear Register
264
Intclear)
264
GPIOD Lower Byte Masked Access Register(GPIOD_ LB_MASKED)
264
GPIOD Upper Byte Masked Access Register(GPIOD_ UB_MASKED)
265
Register Map
266
Table 17 GPIOD Register Map and Reset Values
266
16 Direct Memory Access Controller (DMA)
267
Introduction
267
Features
267
Functional Description
267
Figure 20. DMA Block Diagram
267
DMA Arbitration
268
DMA Cycle Types
268
DMA Request Mapping
268
Table 18 Summary of the DMA Requests for each Channel
268
Figure 21. DMA Ping Pong Cycle
271
DMA Configuration Register (DMA_CFG)
272
DMA Status Register (DMA_STATUS)
272
Registers (Base Address : 0X4100_4000)
272
DMA Channel Alternate Control Data Base Pointer Register
273
DMA Control Data Base Pointer Register (DMA_CTRL_BASE_PTR)
273
(Dma_Alt_Ctrl_Base_Ptr)
273
DMA Channel Wait on Request Status Register (DMA_WAITONREQ_STATUS)
274
DMA Channel Software Request Register (DMA_CHNL_SW_REQUEST)
274
DMA Channel Useburst Set Register (DMA_CHNL_USEBURST_SET)
275
DMA Channel Useburst Clear Register (DMA_CHNL_USEBURST_CLR)
276
DMA Channel Request Mask Set Register (DMA_CHNL_REQ_MASK_SET)
276
DMA Channel Enable Set Register (DMA_CHNL_ENABLE_SET)
277
DMA Channel Request Mask Clear Register (DMA_CHNL_REQ_MASK_CLR)
277
DMA Channel Enable Clear Register (DMA_CHNL_ENABLE_CLR)
278
DMA Channel Primary-Alternate Set Register (DMA_CHNL_PRI_ALT_SET)
278
DMA Channel Primary-Alternate Clear Register (DMA_CHNL_PRI_ALT
279
DMA Channel Priority Clear Register (DMA_CHNL_PRIORITY_CLR)
280
DMA Channel Priority Set Register (DMA_CHNL_PRIORITY_SET)
280
DMA Bus Error Clear Register (DMA_ERR_CLR)
281
Register Map
282
Table 19 DMA Register Map and Reset Values
282
17 Analog-To-Digital Converter (ADC)
283
Introduction
283
Features
283
Functional Description
284
Operation ADC with Non-Interrupt
284
Figure 22. ADC Block Diagram
284
Figure 23. the ADC Operation Flowchart with Non-Interrupt
285
ADC Control Register (ADC_CTR)
286
Figure 24. the ADC Operation Flowchart with Interrupt
286
Operation ADC with Interrupt
286
Registers (Base Address : 0X4100_0000)
286
ADC Channel Select Register (ADC_CHSEL)
287
ADC Conversion Data Register (ADC_DATA)
288
ADC Interrupt Register (ADC_INT)
288
ADC Start Register (ADC_START)
288
ADC Interrupt Clear Register (ADC_INTCLR)
289
Register Map
290
Table 20 ADC Register Map and Reset Values
290
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Wiznet W7500 Reference Manual (399 pages)
W7500 Series
Brand:
Wiznet
| Category:
Controller
| Size: 13.31 MB
Table of Contents
1 Table of Contents
2
2 List of Table
19
3 List of Figures
21
4 Documentation Conventions
23
Glossary
23
Register Bit Conventions
25
5 System and Memory Overview
26
System Architecture
26
Memory Organization
27
Introduction
27
Memory Map
28
6 System Configuration Controller (SYSCFG)
29
7 Interrupt and Events
29
Nested Vectored Interrupt Controller (NVIC)
29
NVIC Main Features
29
Systick Calibration Value Register
29
Interrupt and Exception Vectors
29
Event
30
8 Power Supply
31
Introduction
31
Voltage Regulator
31
Low-Power Modes
31
Sleep Mode
32
Peripheral Clock Gating
32
9 System Tick Timer
33
Introduction
33
Features
33
Functional Description
33
Registers (Base : 0Xe000_E000)
34
System Timer Control and Status Register (SYST_CSR)
34
Systick Reload Value Register (SYST_RVR)
34
Systick Current Value Register (SYST_CVR)
35
Systick Calibration Value Register (SYST_CALIB)
35
10 Booting Sequence
36
11 Embedded Flash Memory
37
Flash Main Features
37
Flash Memory Organization
37
12 Clock Reset Generator (CRG)
39
Introduction
39
Features
39
Reset
39
Clock
40
Functional Description
41
External Oscillator Clock
41
RC Oscillator Clock
42
Pll
42
Generated Clock
42
Registers (Base Address : 0X4100_1000)
44
OSC Power down Register (OSC_PDR)
44
PLL Power down Register (PLL_PDR)
44
PLL Frequency Calculating Register (PLL_FCR)
44
PLL Output Enable Register (PLL_OER)
45
PLL Bypass Register (PLL_BPR)
45
PLL Input Clock Source Select Register (PLL_IFSR)
46
FCLK Source Select Register (FCLK_SSR)
46
FCLK Prescale Value Select Register (FCLK_PVSR)
47
SSPCLK Source Select Register (SSPCLK_SSR)
47
SSPCLK Prescale Value Select Register (SSPCLK_PVSR)
48
ADCCLK Source Select Register (ADCCLK_SSR)
48
ADCCLK Prescale Value Select Register (ADCCLK_PVSR)
48
TIMER0CLK Source Select Register (TIMER0CLK_SSR)
49
TIMER0CLK Prescale Value Select Register (TIMER0CLK_PVSR)
49
TIMER1CLK Source Select Register (TIMER1CLK_SSR)
50
TIMER1CLK Prescale Value Select Register (TIMER1CLK_PVSR)
50
PWM0CLK Source Select Register (PWM0CLK_SSR)
51
PWM0CLK Prescale Value Select Register (PWM0CLK_PVSR)
51
PWM1CLK Source Select Register (PWM1CLK_SSR)
52
PWM1CLK Prescale Value Select Register (PWM1CLK_PVSR)
52
PWM2CLK Source Select Register (PWM2CLK_SSR)
53
PWM2CLK Prescale Value Select Register (PWM2CLK_PVSR)
53
PWM3CLK Source Select Register (PWM3CLK_SSR)
54
PWM3CLK Prescale Value Select Register (PWM3CLK_PVSR)
55
PWM4CLK Source Select Register (PWM4CLK_SSR)
55
PWM4CLK Prescale Value Select Register (PWM4CLK_PVSR)
56
PWM5CLK Source Select Register (PWM5CLK_SSR)
56
PWM5CLK Prescale Value Select Register (PWM5CLK_PVSR)
57
PWM6CLK Source Select Register (PWM6CLK_SSR)
57
PWM6CLK Prescale Value Select Register (PWM6CLK_PVSR)
58
PWM7CLK Source Select Register (PWM7CLK_SSR)
58
PWM7CLK Prescale Value Select Register (PWM7CLK_PVSR)
59
RTC High Speed Source Select Register (RTC_HS_SSR)
59
RTC High Speed Prescale Value Select Register (RTC_HS_PVSR)
60
RTC Source Select Register (RTC_SSR)
60
WDOGCLK High Speed Source Select Register (WDOGCLK_HS_SSR)
61
WDOGCLK High Speed Prescale Value Select Register (WDOGCLK_HS_PVSR)
61
WDOGCLK Clock Source Select Register (WDOGCLK_SSR)
62
UARTCLK Source Select Register (UARTCLK_SSR)
62
UARTCLK Prescale Value Select Register (UARTCLK_PVSR)
63
MIICLK Enable Control Register (MIICLK_ECR)
63
Monitoring Clock Source Select Register (MONCLK_SSR)
64
Register Map
65
13 Tcp/Ip Core Offload Engine (TOE)
67
Introduction
67
Features
67
Functional Description
68
TOE Memory Map
68
Common Register Map
70
Socket Register Map
70
Memory
71
Common Register (Base : 0X4600_0000)
73
VERSIONR (TOE Version Register)
73
TCKCNTR (Ticker Counter Register)
73
IR (Interrupt Register)
74
IMR (Interrupt Mask Register)
74
IRCR (Interrupt Clear Register)
75
SIR (Socket Interrupt Register)
76
SIMR (Socket Interrupt Mask Register)
76
MR (Mode Register)
77
PTIMER (PPP Link Control Protocol Request Timer Register)
78
PMAGICR (PPP Link Control Protocol Magic Number Register)
78
PHAR (Destination Hardware Address Register in Pppoe)
78
PSIDR (Session ID Register in Pppoe)
79
PMRUR (Maximum Receive Unit Register in Pppoe)
80
SHAR (Source Hardware Address Register)
80
GAR (Gateway Address)
81
SUBR ( Subnet Mask Register)
81
SIPR (Source IP Address Register)
82
NCONFLR ( Network Configuration Lock Register)
82
RTR (Retry Time Register)
83
RCR (Retry Counter Register)
84
UIPR (Unreachable IP Address Register)
85
UPORTR (Unreachable Port Register)
86
Socket Register (Base : 0X4601_0000 + 0X0004_000 X N)[N=0
86
Sn_Mr (Socket N Mode Register)
86
Sn_Cr (Socket N Command Register)
89
Sn_Ir (Socket N Interrupt Register)
91
Sn_Imr (Socket N Interrupt Mask Register)
91
Sn_Icr (Socket N Interrupt Clear Register)
92
Sn_Sr (Socket N Status Register)
93
Sn_Pnr (Socket N Protocol Number Register)
95
Sn_Tosr (Socket N IP Type of Service Register)
96
Sn_Ttlr (Socket N TTL Register)
96
Sn_Fragr (Socket N Fragment Offset Register)
97
Sn_Mssr (Socket N Maximum Segment Register)
97
Sn_Portr (Socket N Source Port Register)
98
Sn_Dhar (Socket N Destination Hardware Address Register)
98
Sn_Dportr (Socket N Destination Port Number Register)
99
Sn_Dipr (Socket N Destination IP Address Register)
100
Sn_Katmr (Socket N Keep Alive Timer Register)
101
Sn_Rtr (Socket N Retry Time Register)
101
Sn_Rcr (Socket N Retry Counter Register)
102
Sn_Txbuf_Size (Socket N TX Buffer Size Register)
102
Sn_Tx_Fsr (Socket N TX Free Size Register)
103
Sn_Tx_Rd (Socket N TX Read Pointer Register)
104
Sn_Tx_Wr (Socket N TX Write Pointer Register)
105
Sn_Rxbuf_Size (Socket N RX Buffer Size Register)
105
Sn_Rx_Rsr (Socket N RX Received Size Register)
106
Sn_Rx_Rd (Socket N RX Read Pointer Register)
107
Sn_Rx_Wr (Socket N RX Write Pointer Register)
108
14 Random Number Generator (RNG)
109
Introduction
109
Features
109
Functional Description
109
Operation RNG
110
Registers (Base Address : 0X4000_7000)
111
RNG Run Register (RNG_RUN)
111
RNG SEED Register (RNG_SEED)
111
RNG Clock Select Register (RNG_CLKSEL)
111
RNG Manual Mode Select Register (RNG_MODE)
112
RNG Random Number Value Register (RNG_RN)
112
RNG Polynomial Register (RNG_POLY)
113
Register Map
114
15 Alternate Function Controller (AFC)
114
Introduction
114
Features
114
Functional Description
114
Registers (Base Address : 0X4100_2000)
117
PA_00 Pad Alternate Function Select Register (PA_00_AFR)
117
PA_01 Pad Alternate Function Select Register (PA_01_AFR)
117
PA_02 Pad Alternate Function Select Register (PA_02_AFR)
118
PA_03 Pad Alternate Function Select Register (PA_03_AFR)
118
PA_04 Pad Alternate Function Select Register (PA_04_AFR)
119
PA_05 Pad Alternate Function Select Register (PA_05_AFR)
119
PA_06 Pad Alternate Function Select Register (PA_06_AFR)
120
PA_07 Pad Alternate Function Select Register (PA_07_AFR)
120
PA_08 Pad Alternate Function Select Register (PA_08_AFR)
121
PA_09 Pad Alternate Function Select Register (PA_09_AFR)
121
PA_10 Pad Alternate Function Select Register (PA_10_AFR)
122
PA_11 Pad Alternate Function Select Register (PA_11_AFR)
122
PA_12 Pad Alternate Function Select Register (PA_12_AFR)
123
PA_13 Pad Alternate Function Select Register (PA_13_AFR)
123
PA_14 Pad Alternate Function Select Register (PA_14_AFR)
124
PA_15 Pad Alternate Function Select Register (PA_15_AFR)
124
PB_00 Pad Alternate Function Select Register (PB_00_AFR)
125
PB_01 Pad Alternate Function Select Register (PB_01_AFR)
125
PB_02 Pad Alternate Function Select Register (PB_02_AFR)
126
PB_03 Pad Alternate Function Select Register (PB_03_AFR)
126
PB_04 Pad Alternate Function Select Register (PB_04_AFR)
127
PB_05 Pad Alternate Function Select Register (PB_05_AFR)
127
PB_06 Pad Alternate Function Select Register (PB_06_AFR)
128
PB_07 Pad Alternate Function Select Register (PB_07_AFR)
128
PB_08 Pad Alternate Function Select Register (PB_08_AFR)
129
PB_09 Pad Alternate Function Select Register (PB_09_AFR)
129
PB_10 Pad Alternate Function Select Register (PB_10_AFR)
130
PB_11 Pad Alternate Function Select Register (PB_11_AFR)
130
PB_12 Pad Alternate Function Select Register (PB_12_AFR)
131
PB_13 Pad Alternate Function Select Register (PB_13_AFR)
131
PB_14 Pad Alternate Function Select Register (PB_14_AFR)
132
PB_15 Pad Alternate Function Select Register (PB_15_AFR)
132
PC_00 Pad Alternate Function Select Register (PC_00_AFR)
133
PC_01 Pad Alternate Function Select Register (PC_01_AFR)
133
PC_02 Pad Alternate Function Select Register (PC_02_AFR)
134
PC_03 Pad Alternate Function Select Register (PC_03_AFR)
134
PC_04 Pad Alternate Function Select Register (PC_04_AFR)
135
PC_05 Pad Alternate Function Select Register (PC_05_AFR)
135
PC_06 Pad Alternate Function Select Register (PC_06_AFR)
136
PC_07 Pad Alternate Function Select Register (PC_07_AFR)
136
PC_08 Pad Alternate Function Select Register (PC_08_AFR)
137
PC_09 Pad Alternate Function Select Register (PC_09_AFR)
137
PC_10 Pad Alternate Function Select Register (PC_10_AFR)
138
PC_11 Pad Alternate Function Select Register (PC_11_AFR)
138
PC_12 Pad Alternate Function Select Register (PC_12_AFR)
139
PC_13 Pad Alternate Function Select Register (PC_13_AFR)
139
PC_14 Pad Alternate Function Select Register (PC_14_AFR)
140
PC_15 Pad Alternate Function Select Register (PC_15_AFR)
140
PD_00 Pad Alternate Function Select Register (PD_00_AFR)
141
PD_01 Pad Alternate Function Select Register (PD_01_AFR)
141
PD_02 Pad Alternate Function Select Register (PD_02_AFR)
142
PD_03 Pad Alternate Function Select Register (PD_03_AFR)
142
PD_04 Pad Alternate Function Select Register (PD_04_AFR)
143
Register Map
144
16 External Interrupt (EXTI)
147
Introduction
147
Features
147
Functional Description
147
Registers (Base Address : 0X4100_2000)
149
External Interrupt Enable Register (Px_Y EXTINT)
149
Register Map
149
17 Pad Controller (PADCON)
150
Introduction
150
Features
150
Functional Description
150
Registers (Base Address : 0X4100_3000)
152
PAD Control Register (Px_Y PCR)(X=A..D, Y=0..15
152
Register Map
152
18 General-Purpose I/Os(GPIO)
153
Introduction
153
Features
153
Functional Description
153
Masked Access
154
GPIO Registers(Address Base: 0X4200_0000)
156
GPIO Data Register(Gpiox_Data) (X=A..D
156
GPIO Output Latch Register(Gpiox_Dataout) (X=A..D
156
GPIO Enable Set Register(Gpiox_Outenset) (X=A..D
156
GPIO Enable Clear Register(Gpiox_Outenclr) (X=A..D
157
GPIO Interrupt Enable Set Register(Gpiox_ INTENSET) (X=A..D
157
GPIO Interrupt Enable Clear Register(Gpiox_ INTENCLR) (X=A..D
158
GPIO Interrupt Type Set Register(Gpiox_ INTTYPESET) (X=A..D
158
GPIO Interrupt Type Clear Register(Gpiox_ INTTYPECLR) (X=A..D
159
GPIO Interrupt Polarity Set Register(Gpiox_ INTPOLSET) (X=A..D
159
GPIO Interrupt Polarity Clear Register(Gpiox_ INTPOLCLR) (X=A
160
GPIO Interrupt Status/Clear Register(GPIO_ INTSTATUS/INTCLEAR) (X=A
161
GPIO Lower Byte Masked Access Register(Gpiox_ LB_MASKED) (X=A
161
GPIO Upper Byte Masked Access Register(Gpiox_ UB_MASKED) (X=A
162
Register Map
163
19 Direct Memory Access Controller (DMA)
164
Introduction
164
Features
164
Functional Description
164
DMA Request Mapping
165
DMA Arbitration
165
DMA Cycle Types
165
Registers (Base Address : 0X4100_4000)
168
DMA Status Register (DMA_STATUS)
168
DMA Configuration Register (DMA_CFG)
169
DMA Control Data Base Pointer Register (DMA_CTRL_BASE_PTR)
170
DMA Channel Alternate Control Data Base Pointer Register (DMA_ALT_CTRL_BASE_PTR)
170
DMA Channel Wait on Request Status Register (DMA_WAITONREQ_STATUS)
171
DMA Channel Software Request Register (DMA_CHNL_SW_REQUEST)
171
DMA Channel Useburst Set Register (DMA_CHNL_USEBURST_SET)
172
DMA Channel Useburst Clear Register (DMA_CHNL_USEBURST_CLR)
172
DMA Channel Request Mask Set Register (DMA_CHNL_REQ_MASK_SET)
173
DMA Channel Request Mask Clear Register (DMA_CHNL_REQ_MASK_CLR)
174
DMA Channel Enable Set Register (DMA_CHNL_ENABLE_SET)
174
DMA Channel Enable Clear Register (DMA_CHNL_ENABLE_CLR)
175
DMA Channel Primary-Alternate Set Register (DMA_CHNL_PRI_ALT_SET)
175
DMA Channel Primary-Alternate Clear Register (DMA_CHNL_PRI_ALT
176
DMA Channel Priority Set Register (DMA_CHNL_PRIORITY_SET)
176
DMA Channel Priority Clear Register (DMA_CHNL_PRIORITY_CLR)
177
DMA Bus Error Clear Register (DMA_ERR_CLR)
177
Register Map
179
20 Analog-To-Digital Converter (ADC)
180
Introduction
180
Features
180
Functional Description
181
Operation ADC with Non-Interrupt
181
Operation ADC with Interrupt
183
Registers (Base Address : 0X4100_0000)
183
ADC Control Register (ADC_CTR)
183
ADC Channel Select Register (ADC_CHSEL)
184
ADC Start Register (ADC_START)
185
ADC Conversion Data Register (ADC_DATA)
185
ADC Interrupt Register (ADC_INT)
185
ADC Interrupt Clear Register (ADC_INTCLR)
186
Register Map
187
Wiznet W7500 Information (6 pages)
Revision information
Brand:
Wiznet
| Category:
Microcontrollers
| Size: 0.4 MB
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