User Manuals: WIZnet W7500 ARM Cortex-M0 MCU

Manuals and User Guides for WIZnet W7500 ARM Cortex-M0 MCU. We have 3 WIZnet W7500 ARM Cortex-M0 MCU manuals available for free PDF download: Reference Manual, Information

WIZnet W7500 Reference Manual (512 pages)

Internet Offload Processor

Brand: WIZnet | Category: Computer Hardware | Size: 10 MB

Table of Contents
2
1 Documentation Conventions

29
- List of Abbreviations
  29
- Glossary
  29
- Register Bit Conventions
  31
2 System and Memory Overview

32
- System Architecture
  32
- Figure 1 W7500 System Architecture
  32
- Memory Organization
  33
  - 2.2.1 Introduction
    33
  - 2.2.2 Memory Map
    34
  - Figure 2 W7500 Memory Map
    34
3 System Configuration Controller (SYSCFG)

35
- Introduction
  35
- Registers (Base Address : 0X4001_F000)
  35
  - 3.2.1 REMAP Register
    35
  - 3.2.2 RESETOP Register
    35
  - 3.2.3 RSTINFO Register
    36
4 Interrupt and Events

36
- Introduction
  36
- Interrupt Assignments
  37
- Table 1 W7500 Interrupt Assignments
  37
- Event
  38
5 Power Supply

38
- Introduction
  38
- Voltage Regulator
  38
- Power Supply Supervisor
  38
- Figure 3 por Reset Waveform
  38
- Low-Power Modes
  39
6 System Tick Timer

40
7 Tcpipcore Offload Engine (TOE)

43
8 Booting Sequence

84
- Table 5 Operation of Mode Selection
  84
- Figure 6. Operation of Boot Code
  84
9 Embedded Flash Memory

85
- Flash Main Features
  85
- Flash Memory Functional Description
  85
  - Flash Memory Organization
    85
    
    Table 6 Description of Flash Memory
    85
    
    Read Operations
    87
    
    Figure 7. Flash Reading Sequence
    88
    
    Flash Erase Operations
    88
    
    Figure 8. Flash Erase Operations
    89
    
    Figure 9. Main Flash Memory Programming Sequence
    90
    
    Flash Program Operation
    90
    
    Memory Protection
    91
    
    Read Protection
    91
    
    Write Protection
    91
10 Clock Reset Generator (CRG)

92
11 Random Number Generator (RNG)

117
- Introduction
  117
- Features
  117
- Functional Description
  117
  - Figure 11. Random Number Generator Block Diagram
    117
  - Operation RNG
    118
    
    Figure 12. Flow Chart of RNG Operation
    118
    
    Registers (Base Address : 0X4000_7000)
    119
    
    RNG Clock Select Register (RNG_CLKSEL)
    119
    
    RNG Run Register (RNG_RUN)
    119
    
    RNG SEED Register (RNG_SEED)
    119
    
    RNG Manual Mode Select Register (RNG_MODE)
    120
    
    RNG Random Number Value Register (RNG_RN)
    120
    
    RNG Polynomial Register (RNG_POLY)
    121
    
    Register Map
    122
    
    Table 9 RNG Register Map and Reset Values
    122
12 Alternate Function Controller (AFC)

123
13 External Interrupt (EXTI)

155
14 Pad Controller (PADCON)

189
- Introduction
  189
- Features
  189
- Functional Description
  189
- Figure 14. Function Schematic of Digital I/O Pad
  189
- Registers (Base Address : 0X4100_3000)
  190
  - 14.4.1 PA_00 Pad Control Register
    190
  - Figure 15. Function Schematic of Digital/Analog Mux IO Pad
    190
  - 14.4.2 PA_01 Pad Control Register
    191
  - 14.4.3 PA_02 Pad Control Register
    192
  - 14.4.4 PA_03 Pad Control Register
    192
  - 14.4.5 PA_04 Pad Control Register
    193
  - 14.4.6 PA_05 Pad Control Register
    194
  - 14.4.7 PA_06 Pad Control Register
    194
  - 14.4.8 PA_07 Pad Control Register
    195
  - 14.4.9 PA_08 Pad Control Register
    196
  - PA_09 Pad Control Register
    196
  - PA_10 Pad Control Register
    197
  - PA_11 Pad Control Register
    198
  - PA_12 Pad Control Register
    199
  - PA_13 Pad Control Register
    199
  - PA_14 Pad Control Register
    200
  - PA_15 Pad Control Register
    201
  - PB_00 Pad Control Register
    201
  - PB_01 Pad Control Register
    202
  - PB_02 Pad Control Register
    203
  - PB_03 Pad Control Register
    203
  - PB_04 Pad Control Register
    204
  - PB_05 Pad Control Register
    205
  - PB_06 Pad Control Register
    205
  - PB_07 Pad Control Register
    206
  - PB_08 Pad Control Register
    207
  - PB_09 Pad Control Register
    208
  - PB_10 Pad Control Register
    208
  - PB_11 Pad Control Register
    209
  - PB_12 Pad Control Register
    210
  - PB_13 Pad Control Register
    210
  - PB_14 Pad Control Register
    211
  - PB_15 Pad Control Register
    212
  - PC_00 Pad Control Register
    212
  - PC_01 Pad Control Register
    213
  - PC_02 Pad Control Register
    214
  - PC_03 Pad Control Register
    214
  - PC_04 Pad Control Register
    215
  - PC_05 Pad Control Register
    216
  - PC_06 Pad Control Register
    216
  - PC_07 Pad Control Register
    217
  - PC_08 Pad Control Register
    218
  - PC_09 Pad Control Register
    219
  - PC_10 Pad Control Register
    219
  - PC_11 Pad Control Register
    220
  - PC_12 Pad Control Register
    221
  - PC_13 Pad Control Register
    221
  - PC_14 Pad Control Register
    222
  - PC_15 Pad Control Register
    223
  - PD_00 Pad Control Register
    223
  - PD_01 Pad Control Register
    224
  - PD_02 Pad Control Register
    225
  - PD_03 Pad Control Register
    225
  - PD_04 Pad Control Register
    226
  - Register Map
    228
  - Table 13 PAD Controller Register Map and Reset Values
    228
15 General-Purpose I/Os(GPIO)

232
16 Direct Memory Access Controller (DMA)

267
17 Analog-To-Digital Converter (ADC)

283
- Introduction
  283
- Features
  283
- Functional Description
  284
  - Operation ADC with Non-Interrupt
    284
    
    Figure 22. ADC Block Diagram
    284
    
    Figure 23. the ADC Operation Flowchart with Non-Interrupt
    285
    
    ADC Control Register (ADC_CTR)
    286
    
    Figure 24. the ADC Operation Flowchart with Interrupt
    286
    
    Operation ADC with Interrupt
    286
    
    Registers (Base Address : 0X4100_0000)
    286
    
    ADC Channel Select Register (ADC_CHSEL)
    287
    
    ADC Conversion Data Register (ADC_DATA)
    288
    
    ADC Interrupt Register (ADC_INT)
    288
    
    ADC Start Register (ADC_START)
    288
    
    ADC Interrupt Clear Register (ADC_INTCLR)
    289
    
    Register Map
    290
    
    Table 20 ADC Register Map and Reset Values
    290

Wiznet W7500 Reference Manual (399 pages)

W7500 Series

Brand: Wiznet | Category: Controller | Size: 13 MB

Wiznet W7500 Information (6 pages)

Revision information

Brand: Wiznet | Category: Microcontrollers | Size: 0 MB

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More WIZnet Manuals

User Manuals: WIZnet W7500 ARM Cortex-M0 MCU

WIZnet W7500 Reference Manual (512 pages)

Table of Contents

1 Documentation Conventions

2 System and Memory Overview

3 System Configuration Controller (SYSCFG)

4 Interrupt and Events

5 Power Supply

6 System Tick Timer

7 Tcpipcore Offload Engine (TOE)

8 Booting Sequence

9 Embedded Flash Memory

10 Clock Reset Generator (CRG)

11 Random Number Generator (RNG)

12 Alternate Function Controller (AFC)

13 External Interrupt (EXTI)

14 Pad Controller (PADCON)

15 General-Purpose I/Os(GPIO)

16 Direct Memory Access Controller (DMA)

17 Analog-To-Digital Converter (ADC)

Wiznet W7500 Reference Manual (399 pages)

Table of Contents

1 Table of Contents

2 List of Table

3 List of Figures

4 Documentation Conventions

5 System and Memory Overview

6 System Configuration Controller (SYSCFG)

7 Interrupt and Events

8 Power Supply

9 System Tick Timer

10 Booting Sequence

11 Embedded Flash Memory

12 Clock Reset Generator (CRG)

13 Tcp/Ip Core Offload Engine (TOE)

14 Random Number Generator (RNG)

15 Alternate Function Controller (AFC)

16 External Interrupt (EXTI)

17 Pad Controller (PADCON)

18 General-Purpose I/Os(GPIO)

19 Direct Memory Access Controller (DMA)

20 Analog-To-Digital Converter (ADC)

Wiznet W7500 Information (6 pages)

Table of Contents

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