I2C0 Control Register(I2C0_Ctr) - Wiznet W7500 Reference Manual

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I2C0 Control Register(I2C0_CTR)

Address offset: 0x04

Reset value: 0x0000_0000

[1:0] Reserved, must be kept at reset value

[2] CTREN – Control enable

0: Disable Control mode

By eight bit of slave address

1: Enable Control mode

[3] CTRRWN – Write/Read mode control

0: Write mode

1: Read mode

When CTREN is „1‟, this bit is valid

[4] ADDR10 - Slave address 7bit Select

0: Slave address 7bit select

[5] MODE - Master / Slave Select

0: Slave mode

1: Master mode

[6] INTEREN - Interrupt Enable

0: interrupt disable

1: interrupt enable

[7] COREEN – Core Enable

0: core reset disable

1: core reset enable

[31:8] Reserved, must be kept at reset value

W7500 Datasheet Version1.0.0