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Wiznet W7500 Reference Manual

W7500 series
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W7500x
Reference Manual
Version 1.1.0
http://www.wiznet.io
© Copyright 2018 WIZnet Co., Ltd. All rights reserved.

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  • Page 1 W7500x Reference Manual Version 1.1.0 http://www.wiznet.io © Copyright 2018 WIZnet Co., Ltd. All rights reserved.

  • Page 2: Table Of Contents

    Table of Contents 1 Table of Contents ..................2 2 List of table ..................... 19 3 List of figures................... 21 4 Documentation conventions ................ 23 Glossary ..................23 Register Bit Conventions ..............25 5 System and memory overview ..............26 System architecture ...............
  • Page 3 12 Clock Reset generator (CRG) ................ 39 12.1 Introduction ................. 39 12.2 Features ..................39 Reset....................39 Clock....................40 12.3 Functional description ..............41 External Oscillator Clock ............... 41 RC oscillator clock ................42 PLL....................42 Generated clock .................. 42 12.4 Registers (Base address : 0x4100_1000) ..........
  • Page 4 PWM6CLK source select register (PWM6CLK_SSR) .......... 57 PWM6CLK prescale value select register (PWM6CLK_PVSR) ......58 PWM7CLK source select register (PWM7CLK_SSR) .......... 58 PWM7CLK prescale value select register (PWM7CLK_PVSR) ......59 RTC High Speed source select register (RTC_HS_SSR) ........59 RTC High Speed prescale value select register (RTC_HS_PVSR) ......60 RTC source select register (RTC_SSR) ............
  • Page 5 SUBR ( Subnet Mask Register) ..............81 SIPR (Source IP address Register) ............. 82 NCONFLR ( Network Configuration Lock Register) ......... 82 RTR (Retry Time Register) ..............83 RCR (Retry Counter Register) ..............84 UIPR (Unreachable IP address Register) ............85 UPORTR (Unreachable Port Register) ............
  • Page 6 Operation RNG ................... 110 14.4 Registers (Base address : 0x4000_7000) ..........111 RNG run register (RNG_RUN) ..............111 RNG SEED register (RNG_SEED) ............... 111 RNG clock select register (RNG_CLKSEL) ........... 111 RNG manual mode select register (RNG_MODE) ........... 112 RNG random number value register (RNG_RN) ..........112 RNG polynomial register (RNG_POLY) ............
  • Page 7 PB_09 pad alternate function select register (PB_09_AFR) ......129 PB_10 pad alternate function select register (PB_10_AFR) ......130 PB_11 pad alternate function select register (PB_11_AFR) ......130 PB_12 pad alternate function select register (PB_12_AFR) ......131 PB_13 pad alternate function select register (PB_13_AFR) ......131 PB_14 pad alternate function select register (PB_14_AFR) ......
  • Page 8 17.3 Functional description ..............150 17.4 Registers (Base address : 0x4100_3000) ..........152 PAD Control register (Px_y PCR)(x=A..D, y=0..15) ........152 17.5 Register map ................152 18 General-purpose I/Os(GPIO) ............... 153 18.1 Introduction ................153 18.2 Features ..................153 18.3 Functional description ..............
  • Page 9 DMA channel useburst set register (DMA_CHNL_USEBURST_SET) ....... 172 DMA channel useburst clear register (DMA_CHNL_USEBURST_CLR) ....172 DMA channel request mask set register (DMA_CHNL_REQ_MASK_SET) ....173 DMA channel request mask clear register (DMA_CHNL_REQ_MASK_CLR) ....174 DMA channel enable set register (DMA_CHNL_ENABLE_SET) ......174 DMA channel enable clear register (DMA_CHNL_ENABLE_CLR) ......
  • Page 10 Channel-0 interrupt enable register(PWMCH0IER) ........199 Channel-0 interrupt clear register(PWMCH0ICR) .......... 200 Channel-0 Timer/Counter Register (PWMCH0TCR) ........200 Channel-0 Prescale Counter Register (PWMCH0PCR) ........201 Channel-0 Prescale Register (PWMCH0PR) ..........201 Channel-0 Match Register (PWMCH0MR) ............ 201 Channel-0 Limit Register (PWMCH0LR) ............202 Channel-0 Up-Down Mode Register (PWMCH0UDMR) ........
  • Page 11 Channel-2 interrupt clear register(PWMCH2ICR) .......... 218 Channel-2 Timer/Counter Register (PWMCH2TCR) ........218 Channel-2 Prescale Counter Register (PWMCH2PCR) ........219 Channel-2 Prescale Register (PWMCH2PR) ..........219 Channel-2 Match Register (PWMCH2MR) ............ 220 Channel-2 Limit Register (PWMCH2LR) ............220 Channel-2 Up-Down Mode Register (PWMCH2UDMR) ........220 Channel-2 Timer/Counter Mode Register (PWMCH2TCMR).......
  • Page 12 Channel-4 Timer/Counter Register (PWMCH4TCR) ........236 Channel-4 Prescale Counter Register (PWMCH4PCR) ........237 Channel-4 Prescale Register (PWMCH4PR) ..........237 Channel-4 Match Register (PWMCH4MR) ............ 238 Channel-4 Limit Register (PWMCH4LR) ............238 Channel-4 Up-Down Mode Register (PWMCH4UDMR) ........238 Channel-4 Timer/Counter Mode Register (PWMCH4TCMR)....... 239 Channel-4 PWM output Enable and External input Enable Register (PWMCH4PEEER) Channel-4 Capture Mode Register (PWMCH4CMR) .........
  • Page 13 Channel-6 Prescale Counter Register (PWMCH6PCR) ........255 Channel-6 Prescale Register (PWMCH6PR) ..........255 Channel-6 Match Register (PWMCH6MR) ............ 256 Channel-6 Limit Register (PWMCH6LR) ............256 Channel-6 Up-Down Mode Register (PWMCH6UDMR) ........257 Channel-6 Timer/Counter Mode Register (PWMCH6TCMR)....... 257 Channel-6 PWM output Enable and External input Enable Register (PWMCH6PEEER) Channel-6 Capture Mode Register (PWMCH6CMR) .........
  • Page 14 22.1 Introduction ................275 22.2 Features ..................275 22.3 Functional description ..............276 Clock and clock enable ................ 276 Timer size..................276 Prescaler..................276 Repetition mode................. 276 Interrupt..................277 Operation..................277 How to set the dual timers ..............278 22.4 Dual timer0_0 Registers (Base address : 0x4000_1000) ......
  • Page 15 Timer1_0 Background Load Register (DUALTIMER1_0TimerBGLoad) ....293 22.11 Register map ................295 22.12 Dual timer1_1 Registers (Base address : 0x4000_2020) ......296 Timer1_1 Load Register(DUALTIMER1_1TimerLoad) ........296 Timer1_1 Value Register(DUALTIMER1_1TimerValue) ........296 Timer1_1 Control Register(DUALTIMER1_1TimerControl) ........ 296 Timer1_1 Interrupt Clear Register (DUALTIMER1_1TimerIntClr) ......297 Timer1_1 Raw Interrupt Status Register (DUALTIMER1_1TimerRIS) ....
  • Page 16 RTC control register (RTCCON) ............... 310 RTC Interrupt Mask register (RTCINTE) ............311 RTC Interrupt Pending register (RTCINTP) ..........313 RTC Alarm Mask register (RTCAMR) ............314 RTC BCD Second register (BCDSEC) ............315 RTC BCD Minute register (BCDMIN)............315 RTC BCD Hour register (BCDHOUR) ............
  • Page 17 UART0IMSC (UART0 Interrupt Mask Set/Clear Register) ........336 UART0RIS (UART0 Raw Interrupt Status Register) ......... 338 UART0MIS (UART0 Masked Interrupt Status Register) ........339 UART0ICR (UART0 Interrupt Clear Register) ..........340 25.5 Register map ................341 25.6 UART1 Registers(Base address: 0x4000_D000) ........342 UART1DR (UART1 Data Register) .............
  • Page 18 Interrupt generation logic ..............363 DMA interface ..................363 Interface reset ................... 365 Configuring the SSP ................365 Enable PrimeCell SSP operation .............. 366 Clock ratios ..................366 Programming the SSPCR0 Control Register ..........367 Programming the SSPCR1 Control Register ..........367 Frame format ..................

  • Page 19: List Of Table

    List of table Table 1 W7500x interrupt vector table ............29 Table 2 W7500x sleep mode summary ............32 Table 3 operation of mode selection ............36 Table 4 description of Flash memory ............37 Table 5 CRG register map and reset values ..........67 Table 6.
  • Page 20 Table 38 SSP0 register map and reset values ..........388 Table 39 SSP1 register map and reset values ..........397 20 / 399 W7500x Reference Manual Version1.1.0...

  • Page 21: List Of Figures

    List of figures Figure 1. W7500x System Architecture ............26 Figure 2 W7500x memory map ..............28 Figure 3. operation of boot code .............. 36 Figure 4 CRG block diagram ..............41 Figure 5 Typical application with an 8 MHz crystal ......... 42 Figure 6 TOE block diagram ..............
  • Page 22 Figure 38 The PWM setting flow .............. 198 Figure 39 Block diagram of Dualtimer ............275 Figure 40 The Dual timer setting flow ............278 Figure 41 Watchdog timer operation flow diagram ........303 Figure 42. RTC block diagram ..............308 Figure 43.

  • Page 23: Documentation Conventions

    Documentation conventions Glossary Address Resolution Protocol Advanced High-performance Bus AMBA Advanced Microcontroller Bus Architecture Advanced Peripheral Bus Alternate Function Controller Analog-to-Digital Converter BrownOut Detection Central Processing Unit Clock Reset generator Direct Memory Access End Of Packet EXTINT External Interrupt GPIO General Purpose Input/Output IrDA Infrared Data Association...
  • Page 24 SYSCFG System configuration controller TCPIPCore Offload Engine Transistor-Transistor Logic Transmission Control Protocol UART Universal Asynchronous Receiver/Transmitter Universal Serial Bus User Datagram Protocol Wake On Lan Watchdog Timer 24 / 399 W7500x Reference Manual Version1.1.0...

  • Page 25: Register Bit Conventions

    Register Bit Conventions Each register is shown with a key indicating the accessibility of the each individual bit, and the initial condition: Bit Accessibility Read/Write Read Only Read as 0 Read as 1 Write Only 25 / 399 W7500x Reference Manual Version1.1.0...

  • Page 26: System And Memory Overview

    System and memory overview 5.1 System architecture Main system consists of : Three masters :  Cortex-M0 core TCP/IP Offload Engine uDMAC (PL230, 6channel) Ten slaves :  Internal BOOT ROM Internal SRAM Internal Flash memory Two AHB2APB bridge which connects all APB peripherals Four AHB dedicated to 16bit GPIOs TCPIP Hardware core ...

  • Page 27: Memory Organization

    AHB-Lite BUS This bus connects the Three masters (Cortex-M0 and uDMAC and TCP/IP Offload Engine) and ten AHB slaves. Two APB BUSs These buses connect Seventeen APB peripherals (Watchdog, two Dual timers, PWM, two UARTs, simple UART, two I2Cs, two SSPs, Random Number Generator, Real Time Clock, 12bits Analog Digital Converter, Clock Controller, IO Configuration, PAD MUX controller) 5.2 Memory organization...

  • Page 28: Memory Map

    Memory map Figure 2 W7500x memory map 28 / 399 W7500x Reference Manual Version1.1.0...

  • Page 29: System Configuration Controller (Syscfg)

    System configuration controller (SYSCFG) Main purposes of the system configuration controller are the following Control of the memory remap feature   The ability to enable an automatic reset if the system locks up Information about the cause of the last reset ...

  • Page 30: Event

    settable IRQ[0] SSP0 SSP0 global interrupt 0x0000_0040 Settable IRQ[1] SSP1 SSP1 global interrupt 0x0000_0044 Settable IRQ[2] UART0 UART0 global interrupt 0x0000_0048 Settable IRQ[3] UART1 UART1 global interrupt 0x0000_004C Settable IRQ[4] UART2 UART2 global interrupt 0x0000_0050 Settable IRQ[5] reserved 0x0000_0054 Settable IRQ[6] reserved 0x0000_0058...

  • Page 31: Power Supply

    Power supply 8.1 Introduction W7500x embeds a voltage regulator in order to supply the internal 1.5V digital power domain. Require a 2.7V ~ 5.5V operating supply voltage (VDD)  ADC ref voltage is same as VDD  8.2 Voltage regulator The voltage regulator is always enabled after Reset and works in only one mode.

  • Page 32: Sleep Mode

    Sleep mode W7500x has two kinds of sleep modes. One is Sleep mode and the other is Deep sleep mode. Two of them are almost the same except the clock gated peripherals kinds. Table 2 shows the Sleep mode summary. Table 2 W7500x sleep mode summary Mode Entry...

  • Page 33: System Tick Timer

    System tick timer 9.1 Introduction System tick timer(SysTick) is part of the ARM Cortex-M0 core 9.2 Features Simple 24bit timer. Clocked internally by the system clock. 9.3 Functional description The SysTick timer is an integral part of Cortex-M0. The SysTick timer is intended to generated a fixed 10 millisecond interrupt for use by an operating system or other system management software.

  • Page 34: Registers (Base : 0Xe000_E000)

    9.4 Registers (Base : 0xE000_E000) System Timer control and status register (SYST_CSR) Address Offset : 0x010 Reset value : 0x0000_0000 CNTFLAG TICKINT ENABLE [0] ENABLE – Enables the counter 0 : Counter disabled 1 : Counter enabled [1] TICKINT – Enables SysTick exception request O : Counting down to zero does not assert the SysTick exception request 1 : Counting down to zero to asserts the SysTick exception request [16] COUNTFLAG –...

  • Page 35: Systick Current Value Register (Syst_Cvr)

    To generate a multi-short timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99. SysTick Current Value Register (SYST_CVR) Address Offset : 0x018 Reset value : 0x0000_0000 CURRENT[23:16]...

  • Page 36: Booting Sequence

    Booting Sequence W7500x has three different boot modes that can be selected through the BOOT pin and TEST pin as shown in Table 3. Table 3 operation of mode selection Mode selection Mode Aliasing TEST BOOT User code execute in Main Flash memory. In this mode,W7500x can support ISP function in order to control flash using serial interface.

  • Page 37: Embedded Flash Memory

    Embedded Flash memory 11.1 Flash main features  Up to 128Kbytes of Flash memory Memory organization:  Main Flash memory block:  Up to 128Kbytes Information block:  Up to 512bytes Information block is read only Data block:  Up to 512bytes ...
  • Page 38 0x0003 FF00 ~ 0x0003 FFFF Data1 The W7500 embedded Flash memory can be programmed using in-application programming. IAP allows the user to re-program the Flash memory while the application is running. The program and erase operations can be performed over the whole product voltage range.

  • Page 39: Clock Reset Generator (Crg)

    #define IAP_ERAS_MASS (IAP_ERAS + 5) // Erase all code & data #define IAP_PROG 0x022 This is how to Erase and Program flash memory. Especially, with IAP_ERAS_DAT0 and IAP_ERAS_DAT1, there is no need to put other parameters (there are default values). // Step 1 DATA0 Erase, Read, Write Test DO_IAP(IAP_ERAS_DAT0,0,0,0);...

  • Page 40: Clock

    After remapping   Software reset (SYSRESETREQ bit in Cortex-M0. Refer to the Cortex-M0 technical reference manual for more detail) • Power reset sets all registers to their reset values. • System reset sets all registers to their reset values except the CRG block registers and remap register to protect remap value Clock Two clock sources can be used to drive the system clock.

  • Page 41: Functional Description

    12.3 Functional description Figure 4 shows the CRG block diagram. Figure 4 CRG block diagram External Oscillator Clock The External oscillator clock (OCLK) can be supplied with a 8 to 24 MHz crystal/ceramic resonator oscillator. In the Typical application, Figure 5, �� must be inserted in External ��...

  • Page 42: Rc Oscillator Clock

    For �� and �� , it is recommended to use external ceramic capacitors in the 5 pF to 25 ��������1 ��������2 pF range(typ.) and are usually the same size, designed for application, and selected to match the requirements of the crystal or resonator (see Figure 5). Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).
  • Page 43 PLL output clock (MCLK)   Internal 8MHz RC oscillator clock (RCLK) External oscillator clock (8MHz ~ 24MHz) (OCLK)  Each generated clock has own prescaler which can be selected individually by each prescale value register. FCLK, ADCCLK, SSPCLK, UARTCLK : 1/1, 1/2, 1/4, 1/8 ...

  • Page 44: Registers (Base Address : 0X4100_1000)

    12.4 Registers (Base address : 0x4100_1000) OSC power down register (OSC_PDR) Address offset : 0x000 Reset value : 0x0000_0000 OSCPD [0] OSCPD – Internal 8MHz RC oscillator power down register This bit written by S/W to RCOSC enter sleep mode or not 0 : normal operation 1 : power down (enter sleep mode) PLL power down register (PLL_PDR)

  • Page 45: Pll Output Enable Register (Pll_Oer)

    [1:0] OD [13:8] N [21:16] M These bits are written by S/W to set frequency of PLL output. PLL output frequency FOUT is calculated by the following equations: FOUT = FIN x M / N x 1 / OD Where: M = M[5] x 32 + M[4] x 16 + M[3] x 8 + M[2] x 4 + M[1] x 2 + M[0] x 1 (2 ~ 63) N = N[5] x 32 + N[4] x 16 + N[3] x 8 + N[2] x 4 + N[1] x 2 + N[0] x 1 (1 ~ 63) OD = 2 ^ (2 x OD[1]) x 2 ^ (1 x OD[0])

  • Page 46: Pll Input Clock Source Select Register (Pll_Ifsr)

    PLLBP [0] PLLBP – bypass register of PLL This bit written by S/W to control bypass or not of PLL 0 : bypass disable. Normal operation 1 : bypass enable. Clock out is clock input PLL input clock source select register (PLL_IFSR) Address offset : 0x020 Reset value : 0x0000_0000 PLLIS...

  • Page 47: Fclk Prescale Value Select Register (Fclk_Pvsr)

    00, 01 : output clock of PLL (MCLK) 10 : Internal 8MHz RC oscillator clock (RCLK) 11 : External oscillator clock (OCLK, 8MHz ~ 24MHz) FCLK prescale value select register (FCLK_PVSR) Address offset : 0x034 Reset value : 0x0000_0000 FCKPRE [1:0] FCKPRE –...

  • Page 48: Sspclk Prescale Value Select Register (Sspclk_Pvsr)

    SSPCLK prescale value select register (SSPCLK_PVSR) Address offset : 0x044 Reset value : 0x0000_0000 SSPCP [1:0] SSPCP – select prescale value of SSPCLK clock These bits are written by S/W to select 00 : 1/1 (bypass) 01 : 1/2 10 : 1/4 11 : 1/8 ADCCLK source select register (ADCCLK_SSR) Address offset : 0x060...

  • Page 49: Timer0Clk Source Select Register (Timer0Clk_Ssr)

    ADCCP [1:0] ADCCP – select prescale value of ADCCLK clock These bits are written by S/W to select 00 : 1/1 (bypass) 01 : 1/2 10 : 1/4 11 : 1/8 TIMER0CLK source select register (TIMER0CLK_SSR) Address offset : 0x070 Reset value : 0x0000_0001 T0CSS [1:0] T0CSS –...

  • Page 50: Timer1Clk Source Select Register (Timer1Clk_Ssr)

    T0CPS [2:0] T0CPS – select prescale value of TIM0CLK clock These bits are written by S/W to select 000 : 1/1 (bypass) 001 : 1/2 010 : 1/4 011 : 1/8 100 : 1/16 101 : 1/32 110 : 1/64 111 : 1/128 TIMER1CLK source select register (TIMER1CLK_SSR) Address offset : 0x080...

  • Page 51: Pwm0Clk Source Select Register (Pwm0Clk_Ssr)

    T1CPS [2:0] T1CPS – select prescale value of TIM1CLK clock These bits are written by S/W to select 000 : 1/1 (bypass) 001 : 1/2 010 : 1/4 011 : 1/8 100 : 1/16 101 : 1/32 110 : 1/64 111 : 1/128 PWM0CLK source select register (PWM0CLK_SSR) Address offset : 0x0b0...

  • Page 52: Pwm1Clk Source Select Register (Pwm1Clk_Ssr)

    P0CPS [2:0] P0CPS – select prescale value of PWM0CLK clock These bits are written by S/W to select 000 : 1/1 (bypass) 001 : 1/2 010 : 1/4 011 : 1/8 100 : 1/16 101 : 1/32 110 : 1/64 111 : 1/128 PWM1CLK source select register (PWM1CLK_SSR) Address offset : 0x0c0...

  • Page 53: Pwm2Clk Source Select Register (Pwm2Clk_Ssr)

    P1CPS [2:0] P1CPS – select prescale value of PWM1CLK clock These bits are written by S/W to select 000 : 1/1 (bypass) 001 : 1/2 010 : 1/4 011 : 1/8 100 : 1/16 101 : 1/32 110 : 1/64 111 : 1/128 PWM2CLK source select register (PWM2CLK_SSR) Address offset : 0x0d0...

  • Page 54: Pwm3Clk Source Select Register (Pwm3Clk_Ssr)

    Reset value : 0x0000_0000 P2CPS [2:0] PWM2CLK_PRE – select prescale value of PWM2CLK clock These bits are written by S/W to select 000 : 1/1 (bypass) 001 : 1/2 010 : 1/4 011 : 1/8 100 : 1/16 101 : 1/32 110 : 1/64 111 : 1/128 PWM3CLK source select register (PWM3CLK_SSR)

  • Page 55: Pwm3Clk Prescale Value Select Register (Pwm3Clk_Pvsr)

    PWM3CLK prescale value select register (PWM3CLK_PVSR) Address offset : 0x0e4 Reset value : 0x0000_0000 P3CPS [2:0] P3CPS – select prescale value of PWM3CLK clock These bits are written by S/W to select 000 : 1/1 (bypass) 001 : 1/2 010 : 1/4 011 : 1/8 100 : 1/16 101 : 1/32...

  • Page 56: Pwm4Clk Prescale Value Select Register (Pwm4Clk_Pvsr)

    PWM4CLK prescale value select register (PWM4CLK_PVSR) Address offset : 0x0f4 Reset value : 0x0000_0000 P4CPS [2:0] P4CPS – select prescale value of PWM4CLK clock These bits are written by S/W to select 000 : 1/1 (bypass) 001 : 1/2 010 : 1/4 011 : 1/8 100 : 1/16 101 : 1/32...

  • Page 57: Pwm5Clk Prescale Value Select Register (Pwm5Clk_Pvsr)

    11 : External oscillator clock (OCLK, 8MHz ~ 24MHz) PWM5CLK prescale value select register (PWM5CLK_PVSR) Address offset : 0x104 Reset value : 0x0000_0000 P5CPS [2:0] P5CPS – select prescale value of PWM5CLK clock These bits are written by S/W to select 000 : 1/1 (bypass) 001 : 1/2 010 : 1/4...

  • Page 58: Pwm6Clk Prescale Value Select Register (Pwm6Clk_Pvsr)

    10 : Internal 8MHz RC oscillator clock (RCLK) 11 : External oscillator clock (OCLK, 8MHz ~ 24MHz) PWM6CLK prescale value select register (PWM6CLK_PVSR) Address offset : 0x114 Reset value : 0x0000_0000 P6CPS [2:0] P6CPS – select prescale value of PWM6CLK clock These bits are written by S/W to select 000 : 1/1 (bypass) 001 : 1/2...

  • Page 59: Pwm7Clk Prescale Value Select Register (Pwm7Clk_Pvsr)

    01 : PLL output clock (MCLK) 10 : Internal 8MHz RC oscillator clock (RCLK) 11 : External oscillator clock (OCLK, 8MHz ~ 24MHz) PWM7CLK prescale value select register (PWM7CLK_PVSR) Address offset : 0x124 Reset value : 0x0000_0000 P7CPS [2:0] P7CPS – select prescale value of PWM7CLK clock These bits are written by S/W to select 000 : 1/1 (bypass) 001 : 1/2...

  • Page 60: Rtc High Speed Prescale Value Select Register (Rtc_Hs_Pvsr)

    00 : disable clock 01 : PLL output clock (MCLK) 10 : Internal 8MHz RC oscillator clock (RCLK) 11 : External oscillator clock (OCLK, 8MHz ~ 24MHz) RTC High Speed prescale value select register (RTC_HS_PVSR) Address offset : 0x134 Reset value : 0x0000_0000 RTCPRE [2:0] RTCPRE –...

  • Page 61: Wdogclk High Speed Source Select Register (Wdogclk_Hs_Ssr)

    These bits are written by S/W to select clock source 0 : RTCCLK_hs 1 : 32K_OSC_CLK (Low speed external oscillator clock) WDOGCLK High Speed source select register (WDOGCLK_HS_SSR) Address offset : 0x140 Reset value : 0x0000_0001 WDHS [1:0] WDHS – WDOGCLK_hs clock source select register. These bits are written by S/W to select clock source 00 : disable clock 01 : PLL output clock (MCLK)

  • Page 62: Wdogclk Clock Source Select Register (Wdogclk_Ssr)

    011 : 1/8 100 : 1/16 101 : 1/32 110 : 1/64 111 : 1/128 WDOGCLK clock source select register (WDOGCLK_SSR) Address offset : 0x14c Reset value : 0x0000_0000 WDSEL [0] WDSEL – WDOGCLK clock source select register. These bits are written by S/W to select clock source 0 : WDOGCLK_hs 1 : 32K_OSC_CLK (Low speed external oscillator clock) UARTCLK source select register (UARTCLK_SSR)

  • Page 63: Uartclk Prescale Value Select Register (Uartclk_Pvsr)

    UARTCLK prescale value select register (UARTCLK_PVSR) Address offset : 0x154 Reset value : 0x0000_0000 [1:0] UCP – select prescale value of UARTCLK clock These bits are written by S/W to select 00 : 1/1 (bypass) 01 : 1/2 10 : 1/4 11 : 1/8 MIICLK enable control register (MIICLK_ECR) Address offset : 0x160...

  • Page 64: Monitoring Clock Source Select Register (Monclk_Ssr)

    Monitoring Clock source select register (MONCLK_SSR) Address offset : 0x170 Reset value : 0x0000_0000 CLKMON_SEL [4:0] CLKMON_SEL – Select clock source for monitoring (monitoring pin : PA_02) This bit is written by S/W to set enable or disable 00000 : PLL output clock (MCLK) 00001 : FCLK 00010 : Internal 8MHz RC oscillator clock (RCLK) 00011 : External oscillator clock (OCLK, 8MHz ~ 24MHz)

  • Page 65: Register Map

    12.5 Register map The following table summarizes the CRG registers. Offset Register OSC_PDR 0x000 reset value PLL_PDR 0x010 reset value PLL_FCR 0x014 reset value PLL_OER 0x018 reset value PLL_BPR 0x01c reset value PLL_IFSR 0x020 reset value FCLK_SSR 0x030 reset value FCLK_PVSR 0x034 reset value...
  • Page 66 PWM1CLK_SSR 0x0c0 reset value PWM1CLK_PVSR 0x0c4 reset value PWM2CLK_SSR 0x0d0 reset value PWM2CLK_PVSR 0x0d4 reset value PWM3CLK_SSR 0x0e0 reset value PWM3CLK_PVSR 0x0e4 reset value PWM4CLK_SSR 0x0f0 reset value PWM4CLK_PVSR 0x0f4 reset value PWM5CLK_SSR 0x100 reset value PWM5CLK_PVSR 0x104 reset value PWM6CLK_SSR 0x110 reset value...

  • Page 67: Tcp/Ip Core Offload Engine (Toe)

    Internet connection to embedded systems. TOE enables users to have Internet connectivity in their applications by using the TCP/IP stack. WIZnet’s Hardwired TCP/IP is the market-proven technology that supports TCP, UDP, IPv4, ICMP, ARP, IGMP, and PPPoE protocols. TOE embeds the 32Kbyte internal memory buffer for the Ethernet packet processing.

  • Page 68: Functional Description

    13.3 Functional description Figure 6 shows the TOE block diagram. Figure 6 TOE block diagram 13.4 TOE Memory map TOE has one Common Register Block, eight Socket Register Blocks, and TX/RX Buffer Blocks allocated to each Socket. Figure 7 shows the selected block by the base address and the available offset address range of Socket TX/RX Buffer Blocks.
  • Page 69 Blocks Valid Range: Physical Base address 16bits Offset Address[15:0] 16KB RX Memory 0x3FFF 0xFFFF 0x461F_0000 Socket 7 Socket 7 RX Buffer 0x3E2C RX Buffer (2KB) 0x3800 0xF800 0x461E_0000 Socket 7 TX Buffer 0xF7FF Socket 6 RX Buffer (2KB) 0x461D_0000 Socket 7 Register 0x3000 0xF000 0xEFFF...

  • Page 70: Common Register Map

    Common register map Common Register Block configures the general information of TOE such as IP and MAC address. <Table 6> defines the offset address of registers in this block. Table 6. Offset Address for Common Register Address Register 0x0000 TOE Version (VERSIONR) 0x2000 TICKCLOK (TCLKR) 0x2100...

  • Page 71: Memory

    Table 7. Offset Address in Socket n Register Block (n = 0,…,7, where n is Socket number) Offset Register 0x0000 Socket Mode (Sn_MR) 0x0010 Socket Command (Sn_CR) 0x0020 Socket Interrupt (Sn_IR) 0x0024 Socket Interrupt Mask (Sn_IMR) 0x0028 Socket Interrupt Clear (Sn_ICR) 0x0030 Socket Status (Sn_SR) 0x0100...
  • Page 72 Once all Sn_TXBUF_SIZE registers have been configured, Socket TX Buffer is allocated with the configured size of 16KB TX Memory and is assigned sequentially from Socket 0 to Socket 7. Its physical memory address is automatically determined in 16KB TX memory. Therefore, the total sum of Sn_TXBUF_SIZE should not exceed 16 in case of error in data transmission.

  • Page 73: Common Register (Base : 0X4600_0000)

    13.5 Common register (Base : 0x4600_0000) VERSIONR (TOE Version Register) Address Offset : 0x0000 Reset value : 0x0000_0005 VERSION[7:0] [7:0] VERSION - indicates the TOE version as 0x05. TCKCNTR (Ticker Counter Register) Address Offset : 0x2000 Reset value : 0x0000_07D0 TCKCNT[15:0] [15:0] TCKCNT –...

  • Page 74: Ir (Interrupt Register)

    IR (Interrupt Register) Address Offset : 0x2100 Reset value : 0x0000_0000 IR[7:4] IR indicates the interrupt status. If IR is not equal to ‘0x00’, INTn PIN is asserted low until it is ‘0x00’. [4] WOL – Magic Packet When WOL mode is enabled and receives the magic packet over UDP, this bit is set. [5] PPPoE –...

  • Page 75: Ircr (Interrupt Clear Register)

    IMR is used to mask interrupts. Each bit of IMR corresponds to each bit of IR. When a bit of IMR is ‘1’ and the corresponding bit of IR is ‘1’, an interrupt will be issued. In other words, if a bit of IMR is ‘0’, an interrupt will not be issued even if the corresponding bit of IR is ‘1’.

  • Page 76: Sir (Socket Interrupt Register)

    SIR (Socket Interrupt Register) Address Offset : 0x2110 Reset value : 0x0000_0000 SIR indicates the interrupt status of Socket. Each bit of SIR be still ‘1’ until Sn_IR is cleared by the host. If Sn_IR is not equal to ‘0x00’, the n-th bit of SIR is ‘1’ and INTn PIN is asserted until SIR is ‘0x00’...

  • Page 77: Mr (Mode Register)

    MR (Mode Register) Address Offset : 0x2300 Reset value : 0x0000_0000 MR is used for S/W reset, ping block mode and PPPoE mode [2] NSC – MACRAW No Size Check If this bit is ‘1’, it does not check packet size In MACRAW mode. 0 : Enable Check Packet Size 1 : Disable Check Packet Size [4] PB –...

  • Page 78: Ptimer (Ppp Link Control Protocol Request Timer Register)

    PTIMER (PPP Link Control Protocol Request Timer Register) Address Offset : 0x2400 Reset value : 0x0000_0028 PTIME[7:0] [7:0] PTIME configures the time for sending LCP echo request. The unit of time is 25ms Ex) in case that PTIMER is 200, 200 * 25(ms) = 5000(ms) = 5 seconds PMAGICR (PPP Link Control Protocol Magic number Register) Address Offset : 0x2404...

  • Page 79: Psidr (Session Id Register In Pppoe)

    PHAR[31:24] PHAR1[23:16] PHAR[15:8] PHAR[7:0] Address Offset : 0x240C Reset value : 0x0000_0000 PHAR[31:24] PHAR[23:16] PHAR should be written to the PPPoE server hardware address acquired in PPPoE connection process. PHAR0 and PHAR1 – configures Destination hardware address Ex) In case that destination hardware address is 00:08:DC:12:34:56 PHAR0[32:24] PHAR0[23:16] PHAR0[15:8]...

  • Page 80: Pmrur (Maximum Receive Unit Register In Pppoe)

    [15:0] PSID - should be written to the PPPoE sever session ID acquired in PPPoE connection process. PMRUR (Maximum Receive Unit Register in PPPoE) Address Offset : 0x2414 Reset value : 0x0000_FFFF PMSS[15:0] [15:0] PMRUR configures the maximum receive unit of PPPoE. Ex) in case that maximum receive unit in PPPoE is 0x1234 PMSS[15:8] PMSS[7:0]...

  • Page 81: Gar (Gateway Address)

    SHAR configures the source hardware address. Ex) In case of “00.08.DC.12.34.56” SHAR0[32:24] SHAR0[23:16] SHAR0 [15:8] SHAR0 [32:24] SHAR1 [32:24] SHAR2 [23:16] 0x00 0x08 0xDC 0x12 0x34 0x56 GAR (Gateway Address) Address Offset : 0x6008 Reset value : 0x0000_0000 GA[31:24] GA[23:16] GA[15:8] GA[7:0] GAR[31:0] –...

  • Page 82: Sipr (Source Ip Address Register)

    SUBR[15:8] SUBR[7:0] SUBR configures the subnet mask address. Ex) In case of “255.255.255.0” SUB[31:24] SUB[23:16] SUB[15:8] SUB[7:0] 255 (0xFF) 255 (0xFF) 255 (0xFF) 0 (0x00) SIPR (Source IP address Register) Address Offset : 0x6010 Reset value : 0x0000_0000 [31:24] [23:16] SIPR SIPR [15:8]...

  • Page 83: Rtr (Retry Time Register)

    NCONFL [15:8] NCONFL [7:0] NCONFLR is used to unlock and lock the network configuration registers which are SIR, SUBR, GAR and SHAR. When LOCK is ‘ON’, the protected registers are not able to access. In this case a value of 0x01ACCE55 is written to NCONFLR. When LOCK is ‘OFF’, the protected registers are allowed to access.

  • Page 84: Rcr (Retry Counter Register)

    RTR[15:8] 0x0F RCR (Retry Counter Register) Address Offset : 0x6044 Reset value : 0x0000_0008 RC[7:0] RCR configures the number of time of retransmission. When retransmission occurs as many as ‘RCR+1’, Timeout interrupt is issued (Sn_IR[TIMEOUT] = ‘1’). When RCR is not ‘0x0000_0000, RCR is used to configure the timeout period of all socket. When RCR is ‘0x0000_0000’, the timeout period of each socket could set by using Socket n Retry Counter Register (Sn_RCR).

  • Page 85: Uipr (Unreachable Ip Address Register)

    At the TCP packet retransmission timeout, WZTOE transmits TCP packets (SYN, FIN, RST, DATA packets) and waits for the acknowledgement (ACK) during the configured RTR time and RCR. If there is no ACK from the peer, a temporary timeout occurs and the TCP packet is retransmitted.

  • Page 86: Uportr (Unreachable Port Register)

    TOE receives an ICMP packet(Destination port unreachable) when data is sent to a port number which socket is not open and UNREACH bit of IR becomes ‘1’ and UIPR indicates the destination IP address. Ex) In case of “192.168.0.11” UIP[31:24] UIP[23:16] UIP[15:8] UIP[7:0]...
  • Page 87 Sn_MR[7:0] Sn_MR configures the option or protocol type of Socket n. [3:0] These bits configures the protocol mode of Socket n as follows Sn_MR[3:0] Meaning Closed MACRAW  MACRAW mode should be only used in Socket 0. [4] UNICAST Blocking and IPv6 packet Blocking UNICAST Blocking in UDP mode 0 : disable Unicast Blocking 1 : enable Unicast Blocking...
  • Page 88 Multicast 0 : using IGMP version 2 1 : using IGMP version 1 This bit is applied only during UDP mode(P[3:0] = ‘0010’) and MULTI = ‘1’. It configures the version for IGMP messages (Join/Leave/Report). Multicast Blocking in MACRAW mode 0 : disable Multicast Blocking 1 : enable Multicast Blocking This bit is applied only when MACRAW mode(P[3:0] = ‘0100’).

  • Page 89: Sn_Cr (Socket N Command Register)

    Sn_CR (Socket n Command Register) Address Offset : 0x0010 Reset value : 0x0000_0000 Sn_CR[7:0] This is used to set the command for Socket n such as OPEN, CLOSE, CONNECT, LISTEN, SEND, and RECEIVE. After WZTOE accepts the command, the Sn_CR register is automatically cleared to 0x00.
  • Page 90 to ‘TCP server’ configured by Sn_DIPR & Sn_DPORT(destination address & port). If the connect-request is successful, the Sn_SR is changed to SOCK_ESTABLISHED and the Sn_IR(0) becomes ‘1’. The connect-request fails in the following three cases. 1. When occurs (Sn_IR(3)=‘1’) because destination hardware address is not acquired through the ARP-process.

  • Page 91: Sn_Ir (Socket N Interrupt Register)

    automatic ARP-process(Address Resolution Protocol). SEND_MAC transmits data without the automatic ARP-process. In this case, the destination hardware address is acquired from Sn_DHAR configured by host, instead of APR-process. Valid only in TCP mode. It checks the connection status by sending 1byte keep-alive 0x22 SEND_KEEP packet.

  • Page 92: Sn_Icr (Socket N Interrupt Clear Register)

    Reset value: 0x0000_00FF Sn_IMR[4:0] Sn_IMR is used to mask interrupts. Each bit of Sn_IMR corresponds to each bit of Sn_IR. When a bit of Sn_IMR is ‘1’ and the corresponding bit of Sn_IR is ‘1’, an interrupt will be issued. In other words, if a bit of Sn_IMR is ‘0’, an interrupt will not be issued even if the corresponding bit of Sn_IR is ‘1’.

  • Page 93: Sn_Sr (Socket N Status Register)

    Sn_ICR is used to clear interrupts. Each bit of Sn_IR can be cleared when the host writes ‘1’ value to each bit of Sn_ICR corresponding to each bit of Sn_IR. [0] CONNECT Interrupt Clear [1] DISCONNECT Interrupt Clear [2] RECV Interrupt Mask [3] TIMEOUT Interrupt Mask [4] SENDOK Interrupt Mask ReadClearWrite1 (R/C_W1) : Software can read as well as clear this bit by writing...
  • Page 94 This indicates Socket n is operating as ‘TCP server’ mode and 0x14 SOCK_LISTEN waiting for connection-request (SYN packet) from a peer (‘TCP client’). It will change to SOCK_ESTALBLISHED when the connection- request is successfully accepted. Otherwise it will change to SOCK_CLOSED after TCPTO occurred (Sn_IR(TIMEOUT) = ‘1’).

  • Page 95: Sn_Pnr (Socket N Protocol Number Register)

    It is temporarily shown when Sn_SR is changed from SOCK_INIT to SOCK_ESTABLISHED by CONNECT command. If connect-accept(SYN/ACK packet) is received from the peer at SOCK_SYNSENT, it changes to SOCK_ESTABLISHED. Otherwise, it changes to SOCK_CLOSED after TCPTO (Sn_IR[TIMEOUT] = ‘1’) is occurred. It indicates Socket n successfully received the connect- 0x16 SOCK_SYNRECV...

  • Page 96: Sn_Tosr (Socket N Ip Type Of Service Register)

    overall list of upper level protocol identification number that IP is using, refer to online documents of IANA (http://www.iana.org/assignments/protocol-numbers). Ex) Internet Control Message Protocol (ICMP) = 0x01, Internet Group Management Protocol = 0x02 Sn_TOSR (Socket n IP Type of Service Register) Address Offset : 0x0104 Reset value : 0x0000_0000 Sn_ROS[7:0]...

  • Page 97: Sn_Fragr (Socket N Fragment Offset Register)

    Sn_FRAGR (Socket n Fragment offset Register) Address Offset : 0x010C Reset value : 0x0000_4000 Sn_FRAG[15:0] [15:0] Sn_FRAG configures the FRAG(Fragment field in IP header) Ex) Sn_FRAGR = 0x0000 (Don’t Fragment) Sn_FRAG[15:8] Sn_FRAG[7:0] 0x00 0x00 Sn_MSSR (Socket n Maximum Segment Register) Address Offset : 0x0110 Reset value : 0x0000_0000 Sn_MSS[15:0]...

  • Page 98: Sn_Portr (Socket N Source Port Register)

    Sn_PORTR (Socket n Source Port Register) Address Offset : 0x0114 Reset value : 0x0000_0000 Sn_PORT[15:0] Sn_PORTR configures the source port number of Socket n. It is valid when Socket n is used in TCP/UDP mode. It should be set before OPEN command is ordered. Ex) In case of Socket 0 Port = 5000(0x1388), configure as below, 0x4101_0114 0x1388...

  • Page 99: Sn_Dportr (Socket N Destination Port Number Register)

    Sn_DHAR1 [15:8] Sn_DHAR1 [7:0] Sn_DHAR configures the destination hardware address of Socket n when using SEND_MAC command in UDP mode or it indicates that it is acquired in ARP-process by CONNECT/SEND command. Ex) In case of writing MAC address “00.08.DC.12.34.56” Sn_DHAR0 Sn_DHAR0 Sn_DHAR0...

  • Page 100: Sn_Dipr (Socket N Destination Ip Address Register)

    In TCP client mode, it configures the listen port number of ‘TCP server’ before CONNECT command. In TCP server mode, it indicates the port number of ‘TCP client’ after successfully establishing connection. In UDP mode, it configures the port number of peer to be transmitted the UDP packet by SEND/SEND_MAC command.

  • Page 101: Sn_Katmr (Socket N Keep Alive Timer Register)

    Sn_KATMR (Socket n Keep Alive Timer Register) Address Offset : 0x0180 Reset value : 0x0000_0000 Sn_KATM[7:0] Sn_KPALVTR configures the transmitting timer of ‘KEEP ALIVE(KA)’ packet of SOCKETn. It is valid only in TCP mode, and ignored in other modes. The time unit is 5s(Refer to TCKCNTR). KA packet is transmittable after Sn_SR is changed to SOCK_ESTABLISHED and after the data is transmitted to a peer at least once.

  • Page 102: Sn_Rcr (Socket N Retry Counter Register)

    During the time configured by Sn_RTR, WZTOE waits for the peer response to the packet that is transmitted by Sn_CR(CONNECT, DISCON, CLOSE, SEND, SEND_MAC, SEND_KEEP command). If the peer does not respond within the RTR time, WZTOE retransmits the packet or issues timeout.

  • Page 103: Sn_Tx_Fsr (Socket N Tx Free Size Register)

    Sn_TMS[7:0] Sn_TXBUF_SIZE configures the TX Buffer size of Socket n. Socket n TX Buffer size can be configured with 0,1,2,4,8 and 16 Kbytes. If a different size is configured, the data can’t be normally transmitted to a peer. Although Socket n TX Buffer size is initially configured to 2Kbytes, user can be re-configure its size using Sn_TXBUF_SIZE.

  • Page 104: Sn_Tx_Rd (Socket N Tx Read Pointer Register)

    because the bigger data overwrites the previous saved data not yet sent. Therefore, check before saving the data to the Socket n TX Buffer, and if data is equal or smaller than its checked size, transmit the data with SEND/SEND_MAC command after saving the data in Socket n TX Buffer.

  • Page 105: Sn_Tx_Wr (Socket N Tx Write Pointer Register)

    After its initialization, it is auto-increased by SEND command. SEND command transmits the saved data from the current Sn_TX_RD to the Sn_TX_WR in the Socket n TX Memory. After transmitting the saved data, the SEND command increases the Sn_TX_RD as same as the Sn_TX_WR.

  • Page 106: Sn_Rx_Rsr (Socket N Rx Received Size Register)

    Sn_RXMS[15:0] Sn_RXBUF_SIZE configures the RX Buffer size of Socket n. Socket n RX Buffer size can be configured with 1,2,4,8, and 16 Kbytes. If a different size is configured, the data cannot be normally received from a peer. Although Socket n RX Buffer size is initially configured to 2Kbytes, user can re-configure its size using Sn_RXBUF_SIZE.

  • Page 107: Sn_Rx_Rd (Socket N Rx Read Pointer Register)

    Ex) In case of 2048(0x0800) in S0_RXSR, 0x4101_0224 0x0800 Note) Because this register for representing the size information is 16 bits, it is impossible to read all bytes at the same time. Before 16 bit-read operation is not completed, the value may be changed.

  • Page 108: Sn_Rx_Wr (Socket N Rx Write Pointer Register)

    Sn_RX_WR (Socket n RX Write Pointer Register) Address Offset : 0x022C Reset value : 0x0000_0000 Sn_RX_WR[15:0] Sn_RX_WR is initialized by OPEN command and it is auto-increased by the data reception. If the increased value exceeds the maximum value 0xFFFF, (greater than 0x10000 and the carry bit occurs), then the carry bit is ignored and will automatically update with the lower 16bits value.

  • Page 109: Random Number Generator (Rng)

    Random number generator (RNG) 14.1 Introduction RNG is a 32bit random number generator. RNG generates power on random number when power on reset. RNG can run/stop by software. RNG seed value and polynomial of RNG can be modified by software. 14.2 Features •...

  • Page 110: Operation Rng

    Operation RNG Figure 9 shows the flowchart of RNG operation. A random number is automatically generated after powering on reset, Follow the procedure below to manually generate a random number. 1. Change MODE to start/stop by register. 2. Change clock source / seed value / polynomial value if need. 3.

  • Page 111: Registers (Base Address : 0X4000_7000)

    14.4 Registers (Base address : 0x4000_7000) RNG run register (RNG_RUN) Address offset : 0x000 Reset value : 0x0000_0000 [0] RUN – run RNG shift register This bit written by S/W to run or stop RNG 0 : stop random number generator shift register 1 : run random number generator shift register RNG SEED register (RNG_SEED) Address offset : 0x004...

  • Page 112: Rng Manual Mode Select Register (Rng_Mode)

    CLKSEL [0] CLKSEL – select clock source register of RNG shift register This bit written by S/W to select clock source of RNG shift register 0 : RNG clock (refer to clock generator block) 1 : PCLK RNG manual mode select register (RNG_MODE) Address offset : 0x00c Reset value : 0x0000_0000 MODE...

  • Page 113: Rng Polynomial Register (Rng_Poly)

    RN[15:0] [31:0] RN – random number of RNG shift register These bits are read only registers. RNG polynomial register (RNG_POLY) Address offset : 0x014 Reset value : 0xE000_0202 POLY[31:16] POLY[15:0] [31:0] POLY – 32bit polynomial of random number generator These bits are written by S/W to modify the formula of random number generator Default polynomial: F(x) = x 113 / 399 W7500x Reference Manual Version1.1.0...

  • Page 114: Register Map

    14.5 Register map The following Table 8 summarizes the RNG registers. Table 8 RNG register map and reset values Offset Register RNG_RUN 0x000 reset value SEED RNG_SEED 0x004 reset value RNG_CLKSEL 0x008 reset value RNG_MODE 0x00C reset value RNG_RN 0x010 reset value POLY RNG_POLY...
  • Page 115 W7500 PA_00 GPIOA_0 PWM6/CAP6 W7500P W7500 PA_01 GPIOA_1 PWM7/CAP7 W7500P W7500 PA_02 GPIOA_2 CLKOUT W7500P W7500 PA_03 SWCLK PWM0/CAP0 W7500P W7500 PA_04 SWDIO PWM1/CAP1 W7500P W7500 PA_05 SSEL0 SCL1 PWM2/CAP2 W7500P W7500 PA_06 SCLK0 SDA1 PWM3/CAP3 W7500P W7500 PA_07 MISO0...
  • Page 116 PB_03 W7500P MOSI1 GPIOB_3 U_RXD0 PB_04 W7500 TXEN GPIOB_4 PB_05 W7500 GPIOB_5 W7500 RXD3 GPIOB_6 PB_06 W7500P PB_07 W7500 RXCLK GPIOB_7 PB_08 W7500 GPIOB_8 PB_09 W7500 TXCLK GPIOB_9 PB_10 W7500 TXD0 GPIOB_10 PB_11 W7500 TXD1 GPIOB_11 PB_12 W7500 TXD2 GPIOB_12...

  • Page 117: Registers (Base Address : 0X4100_2000)

    PC_12 W7500P AIN3 GPIOC_12 SSEL0 AIN3 W7500 PC_13 AIN2 GPIOC_13 SCLK0 AIN2 W7500P W7500 PC_14 AIN1 GPIOC_14 MISO0 AIN1 W7500P W7500 PC_15 AIN0 GPIOC_15 MOSI0 AIN0 W7500P PD_00 W7500 GPIOD_0 PD_01 W7500 RXDV GPIOD_1 PD_02 W7500 RXD0 GPIOD_2 PD_03 W7500...

  • Page 118: Pa_02 Pad Alternate Function Select Register (Pa_02_Afr)

    PA01AF [1:0] PA01AF – PA_01 Pad function selection register. These bits are written by S/W. 00 : GPIOA_1 01 : GPIOA_1 10 : PWM7/CAP7 11 : None PA_02 pad alternate function select register (PA_02_AFR) Address offset : 0x008 Reset value : 0x0000_0000 PA02AF [1:0] PA02AF –...

  • Page 119: Pa_04 Pad Alternate Function Select Register (Pa_04_Afr)

    PA03AF [1:0] PA03AF – PA_03 Pad function selection register. These bits are written by S/W. 00 : SWCLK 01 : GPIOA_3 10 : None 11 : PWM0/CAP0 PA_04 pad alternate function select register (PA_04_AFR) Address offset : 0x010 Reset value : 0x0000_0000 PA04AF [1:0] PA04AF –...

  • Page 120: Pa_06 Pad Alternate Function Select Register (Pa_06_Afr)

    PA05AF [1:0] PA05AF – PA_05 Pad function selection register. These bits are written by S/W. 00 : SSEL0 01 : GPIOA_5 10 : SCL1 11 : PWM2/CAP2 PA_06 pad alternate function select register (PA_06_AFR) Address offset : 0x018 Reset value : 0x0000_0000 PA06AF [1:0] PA06AF –...

  • Page 121: Pa_08 Pad Alternate Function Select Register (Pa_08_Afr)

    PA07AF [1:0] PA07AF – PA_07 Pad function selection register. These bits are written by S/W. 00 : MISO0 01 : GPIOA_7 10 : CTS1 11 : PWM4/CAP4 PA_08 pad alternate function select register (PA_08_AFR) Address offset : 0x020 Reset value : 0x0000_0000 PA08AF [1:0] PA08AF –...

  • Page 122: Pa_10 Pad Alternate Function Select Register (Pa_10_Afr)

    PA09AF [1:0] PA09AF – PA_09 Pad function selection register. These bits are written by S/W. 00 : SCL0 01 : GPIOA_9 10 : TXD1 11 : PWM6/CAP6 PA_10 pad alternate function select register (PA_10_AFR) Address offset : 0x028 Reset value : 0x0000_0000 PA10AF [1:0] PA10AF –...

  • Page 123: Pa_12 Pad Alternate Function Select Register (Pa_12_Afr)

    PA11AF [1:0] PA11AF – PA_11 Pad function selection register. These bits are written by S/W. 00 : CTS0 01 : GPIOA_11 10 : SSEL1 11 : None PA_12 pad alternate function select register (PA_12_AFR) Address offset : 0x030 Reset value : 0x0000_0000 PA12AF [1:0] PA12AF –...

  • Page 124: Pa_14 Pad Alternate Function Select Register (Pa_14_Afr)

    PA13AF [1:0] PA13AF – PA_13 Pad function selection register. These bits are written by S/W. 00 : TXD0 01 : GPIOA_13 10 : MISO1 11 : None PA_14 pad alternate function select register (PA_14_AFR) Address offset : 0x038 Reset value : 0x0000_0000 PA14AF [1:0] PA14AF –...

  • Page 125: Pb_00 Pad Alternate Function Select Register (Pb_00_Afr)

    PA15AF [1:0] PA15AF – PA_15 Pad function selection register. These bits are written by S/W. 00 : GPIOA_15 01 : GPIOA_15 10 : None 11 : None PB_00 pad alternate function select register (PB_00_AFR) Address offset : 0x040 Reset value : 0x0000_0000 PB00AF [1:0] PB00AF –...

  • Page 126: Pb_02 Pad Alternate Function Select Register (Pb_02_Afr)

    PB01AF [1:0] PB01AF – PB_01 Pad function selection register. These bits are written by S/W. 00 : SCLK1 01 : GPIOB_1 10 : RTS0 11 : None PB_02 pad alternate function select register (PB_02_AFR) Address offset : 0x048 Reset value : 0x0000_0000 PB02AF [1:0] PB02AF –...

  • Page 127: Pb_04 Pad Alternate Function Select Register (Pb_04_Afr)

    [1:0] PB03AF – PB_03 Pad function selection register. These bits are written by S/W. 00 : MOSI1 01 : GPIOB_3 10 : RXD0 11 : None PB_04 pad alternate function select register (PB_04_AFR) Address offset : 0x050 Reset value : 0x0000_0000 PB04AF [1:0] PB04AF –...

  • Page 128: Pb_06 Pad Alternate Function Select Register (Pb_06_Afr)

    [1:0] PB05AF – PB_05 Pad function selection register. These bits are written by S/W. 00 : COL 01 : GPIOB_5 10 : None 11 : None PB_06 pad alternate function select register (PB_06_AFR) Address offset : 0x058 Reset value : 0x0000_0000 PB06AF [1:0] PB06AF –...

  • Page 129: Pb_08 Pad Alternate Function Select Register (Pb_08_Afr)

    [1:0] PB07AF – PB_07 Pad function selection register. These bits are written by S/W. 00 : RXCLK 01 : GPIOB_7 10 : None 11 : None PB_08 pad alternate function select register (PB_08_AFR) Address offset : 0x060 Reset value : 0x0000_0000 PB08AF [1:0] PB08AF –...

  • Page 130: Pb_10 Pad Alternate Function Select Register (Pb_10_Afr)

    [1:0] PB09AF – PB_09 Pad function selection register. These bits are written by S/W. 00 : TXCLK 01 : GPIOB_9 10 : None 11 : None PB_10 pad alternate function select register (PB_10_AFR) Address offset : 0x068 Reset value : 0x0000_0000 PB10AF [1:0] PB10AF –...

  • Page 131: Pb_12 Pad Alternate Function Select Register (Pb_12_Afr)

    [1:0] PB11AF – PB_11 Pad function selection register. These bits are written by S/W. 00 : TXD1 01 : GPIOB_11 10 : None 11 : None PB_12 pad alternate function select register (PB_12_AFR) Address offset : 0x070 Reset value : 0x0000_0000 PB12AF [1:0] PB12AF –...

  • Page 132: Pb_14 Pad Alternate Function Select Register (Pb_14_Afr)

    These bits are written by S/W. 00 : TXD3 01 : GPIOB_13 10 : None 11 : None PB_14 pad alternate function select register (PB_14_AFR) Address offset : 0x078 Reset value : 0x0000_0000 PB14AF [1:0] PB14AF – PB_14 Pad function selection register. These bits are written by S/W.

  • Page 133: Pc_00 Pad Alternate Function Select Register (Pc_00_Afr)

    00 : MDC 01 : GPIOB_15 10 : None 11 : None PC_00 pad alternate function select register (PC_00_AFR) Address offset : 0x080 Reset value : 0x0000_0000 PC00AF [1:0] PC00AF – PC_00 Pad function selection register. These bits are written by S/W. 00 : CTS1 01 : GPIOC_0 10 : PWM0/CAP0...

  • Page 134: Pc_02 Pad Alternate Function Select Register (Pc_02_Afr)

    01 : GPIOC_1 10 : PWM1/CAP1 11 : None PC_02 pad alternate function select register (PC_02_AFR) Address offset : 0x088 Reset value : 0x0000_0000 PC02AF [1:0] PC02AF – PC_02 Pad function selection register. These bits are written by S/W. 00 : TXD1 01 : GPIOC_2 10 : PWM2/CAP2 11 : None...

  • Page 135: Pc_04 Pad Alternate Function Select Register (Pc_04_Afr)

    00 : RXD1 01 : GPIOC_3 10 : PWM3/CAP3 11 : None PC_04 pad alternate function select register (PC_04_AFR) Address offset : 0x090 Reset value : 0x0000_0000 PC04AF [1:0] PC04AF – PC_04 Pad function selection register. These bits are written by S/W. 00 : SCL1 01 : GPIOC_4 10 : PWM4/CAP4...

  • Page 136: Pc_06 Pad Alternate Function Select Register (Pc_06_Afr)

    01 : GPIOC_5 10 : PWM5/CAP5 11 : None PC_06 pad alternate function select register (PC_06_AFR) Address offset : 0x098 Reset value : 0x0000_0000 PC06AF [1:0] PC06AF – PC_06 Pad function selection register. These bits are written by S/W. 00 : GPIOC_6 01 : GPIOC_6 10 : TXD2 11 : None...

  • Page 137: Pc_08 Pad Alternate Function Select Register (Pc_08_Afr)

    10 : RXD2 11 : None PC_08 pad alternate function select register (PC_08_AFR) Address offset : 0x0a0 Reset value : 0x0000_0000 PC08AF [1:0] PC08AF – PC_08 Pad function selection register. These bits are written by S/W. 00 : PWM0/CAP0 01 : GPIOC_8 10 : SCL0 11 : ADC_IN7 PC_09 pad alternate function select register (PC_09_AFR)

  • Page 138: Pc_10 Pad Alternate Function Select Register (Pc_10_Afr)

    11 : ADC_IN6 PC_10 pad alternate function select register (PC_10_AFR) Address offset : 0x0a8 Reset value : 0x0000_0000 PC10AF [1:0] PC10AF – PC_10 Pad function selection register. These bits are written by S/W. 00 : TXD2 01 : GPIOC_10 10 : PWM2/CAP2 11 : ADC_IN5 PC_11 pad alternate function select register (PC_11_AFR) Address offset : 0x0ac...

  • Page 139: Pc_12 Pad Alternate Function Select Register (Pc_12_Afr)

    PC_12 pad alternate function select register (PC_12_AFR) Address offset : 0x0b0 Reset value : 0x0000_0000 PC12AF [1:0] PC12AF – PC_12 Pad function selection register. These bits are written by S/W. 00 : ADC_IN3 01 : GPIOC_12 10 : SSEL0 11 : ADC_IN3 PC_13 pad alternate function select register (PC_13_AFR) Address offset : 0x0b4 Reset value : 0x0000_0000...

  • Page 140: Pc_14 Pad Alternate Function Select Register (Pc_14_Afr)

    PC_14 pad alternate function select register (PC_14_AFR) Address offset : 0x0b8 Reset value : 0x0000_0000 PC14AF [1:0] PC14AF – PC_14 Pad function selection register. These bits are written by S/W. 00 : ADC_IN1 01 : GPIOC_14 10 : MISO0 11 : ADC_IN1 PC_15 pad alternate function select register (PC_15_AFR) Address offset : 0x0bc Reset value : 0x0000_0000...

  • Page 141: Pd_00 Pad Alternate Function Select Register (Pd_00_Afr)

    PD_00 pad alternate function select register (PD_00_AFR) Address offset : 0x0c0 Reset value : 0x0000_0000 PD00AF [1:0] PD00AF – PD_00 Pad function selection register. These bits are written by S/W. 00 : CRS 01 : GPIOD_0 10 : None 11 : None PD_01 pad alternate function select register (PD_01_AFR) Address offset : 0x0c4 Reset value : 0x0000_0000...

  • Page 142: Pd_02 Pad Alternate Function Select Register (Pd_02_Afr)

    PD_02 pad alternate function select register (PD_02_AFR) Address offset : 0x0c8 Reset value : 0x0000_0000 PD02AF [1:0] PD02AF – PD_02 Pad function selection register. These bits are written by S/W. 00 : RXD0 01 : GPIOD_2 10 : None 11 : None PD_03 pad alternate function select register (PD_03_AFR) Address offset : 0x0cc Reset value : 0x0000_0000...

  • Page 143: Pd_04 Pad Alternate Function Select Register (Pd_04_Afr)

    PD_04 pad alternate function select register (PD_04_AFR) Address offset : 0x0d0 Reset value : 0x0000_0000 PD04AF [1:0] PD04AF – PD_04 Pad function selection register. These bits are written by S/W. 00 : RXD2 01 : GPIOD_4 10 : None 11 : None 143 / 399 W7500x Reference Manual Version1.1.0...

  • Page 144: Register Map

    15.5 Register map The following Table 10 summarizes the AFC registers. Table 10 AFC register map and reset values Offset Register PA_00_AFR 0x000 reset value PA_01_AFR 0x004 reset value PA_02_AFR 0x008 reset value PA_03_AFR 0x00c reset value PA_04_AFR 0x010 reset value PA_05_AFR 0x014 reset value...
  • Page 145 PB_02_AFR 0x048 reset value PB_03_AFR 0x04c reset value PB_04_AFR 0x050 reset value PB_05_AFR 0x054 reset value PB_06_AFR 0x058 reset value PB_07_AFR 0x05c reset value PB_08_AFR 0x060 reset value PB_09_AFR 0x064 reset value PB_10_AFR 0x068 reset value PB_11_AFR 0x06c reset value PB_12_AFR 0x070 reset value...
  • Page 146 PC_06_AFR 0x098 reset value PC_07_AFR 0x09c reset value PC_08_AFR 0x0a0 reset value PC_09_AFR 0x0a4 reset value PC_10_AFR 0x0a8 reset value PC_11_AFR 0x0ac reset value PC_12_AFR 0x0b0 reset value PC_13_AFR 0x0b4 reset value PC_14_AFR 0x0b8 reset value PC_15_AFR 0x0bc reset value PD_00_AFR 0x0c0 reset value...

  • Page 147: External Interrupt (Exti)

    External Interrupt (EXTI) 16.1 Introduction Each functional pads are connected to the external interrupt(EXTINT) source. 16.2 Features • All functional pads can be used as an external interrupt source regardless of any set of pad function. • External Interrupt controller has the following functions and can be controlled by registers. Interrupt mask (enable or disable, default : disable) ...
  • Page 148 PA_00_mask PA_00 PA_00_Polarity PA_14_mask PA_14 PA_14_Polarity PB_00_mask PB_00 PB_00_Polarity PB_03_mask EXTINT PB_03 PB_03_Polarity PC_00_mask PC_00 PC_00_Polarity PC_06_mask PC_06 PC_06_Polarity PC_08_mask PC_08 PC_08_Polarity PC_15_mask PC_15 PC_15_Polarity Figure 10. External Interrupt diagram 148 / 399 W7500x Reference Manual Version1.1.0...

  • Page 149: Registers (Base Address : 0X4100_2000)

    16.4 Registers (Base address : 0x4100_2000) External interrupt enable register (Px_y EXTINT) Address offset : 0x200 Reset value : 0x0000_0000 [0] POL – External interrupt polarity selection register These bits are written by S/W. 0 : interrupt occurs when pad detect HIGH level signal 1 : interrupt occurs when pad detect LOW level signal [1] PA00IEN –...

  • Page 150: Pad Controller (Padcon)

    Pad Controller (PADCON) 17.1 Introduction Pads of W7500x are controllable. User can control pad’s characteristic. 17.2 Features • W7500x has digital I/O pads and digital/analog mux I/O pads • Controllable characteristics of pads are pull-up, pull-down, driving strength, input enable, and CMOS/Schmitt trigger input buffer •...
  • Page 151 Initials of Pad diagram is same as below. P - PAD YA – Analog Input (connect to ADC input) Y – Digital Input IE – Input buffer enable Condition Output mode Input buffer enable (IE = 1) Input mode No use Output mode Low (0) Input buffer disable...

  • Page 152: Registers (Base Address : 0X4100_3000)

    17.4 Registers (Base address : 0x4100_3000) PAD Control register (Px_y PCR)(x=A..D, y=0..15) Address offset : 0x000 Reset value : 0x0000_0060 PUPD [1:0] PUPD – Pull-up, Pull-down selection register These bits are written by S/W. 00 : Neither 01 : pull-down 10 : pull-up 11 : Neither [2] DS –...

  • Page 153: General-Purpose I/Os(Gpio)

    General-purpose I/Os(GPIO) 18.1 Introduction The GPIO(General-Purpose I/O Port) is composed of three physical GPIO blocks, each corresponding to an individual GPIO port(PORT A, PORT B and PORT C). The GPIO supports up to 34 programmable input/output pins, depending on the peripherals being used. 18.2 Features The GPIO peripheral consists the following features.

  • Page 154: Masked Access

    The pad control supports pull-down, pull-up, input buffer, and summit trigger input buffer. Refer to ‘Pad Controller (PADCON)’ for more details about each register. Initia l setting Sta rt GPIO Mode = GPIO mode Out ? Set GPIOxOUTENSET Set GPIOxOUTENCLR Set PADCON Set PADCON Receive DATA...
  • Page 155 Address offset Upper byte masked access register DATAOUT = 0x322B 0x0800 Address offset = 0x0400 + 0xC3*4 = 0x70C MASKLOWBYTE is a data MASK_LOWBYTE[0xC3] = 0x03 lower byte masked array of 32-bit x 256 access register bit mask : 'b1100_0011(0xC3) 0x0400 set bit[1:0] to 1 clear bit[7:6] to 0...

  • Page 156: Gpio Registers(Address Base: 0X4200_0000)

    18.4 GPIO Registers(Address Base: 0x4200_0000) GPIO Data Register(GPIOx_DATA) (x=A..D) Address offset: 0x0000 Reset value: 0x---- DAT9 DAT8 DAT7 DAT6 DAT5 DAT4 DAT3 DAT2 DAT1 DAT0 DAT15 DAT14 DAT13 DAT12 DAT11 DAT10 [15:0] DATy(y = 0..15) READ as : Port input data bit GPIO Output Latch Register(GPIOx_DATAOUT) (x=A..D) Address offset: 0x0004 Reset value: 0x----...

  • Page 157: Gpio Enable Clear Register(Gpiox_Outenclr) (X=A..d

    ES15 ES14 ES13 ES12 ES11 ES10 [15:0] ESy(y = 0..15) WRITE as : ‘0’ is no effect ‘1’ is sets the corresponding output enable bit READ as : ‘0’ is indicates the signal direction as input ‘1’ is indicates the signal direction as output GPIO Enable Clear Register(GPIOx_OUTENCLR) (x=A..D) Address offset: 0x0014 Reset value: 0x0000...

  • Page 158: Gpio Interrupt Enable Clear Register(Gpiox_ Intenclr) (X=A..d

    IES15 IES14 IES13 IES12 IES11 IES10 IES9 IES8 IES7 IES6 IES5 IES4 IES3 IES2 IES1 IES0 [15:0] IESy(y = 0..15) WRITE as : ‘0’ is no effect ‘1’ is sets the interrupt enable bit READ as : ‘0’ is indicates the interrupt disable ‘1’...

  • Page 159: Gpio Interrupt Type Clear Register(Gpiox_ Inttypeclr) (X=A..d

    ITS15 ITS14 ITS13 ITS12 ITS11 ITS10 ITS9 ITS8 ITS7 ITS6 ITS5 ITS4 ITS3 ITS2 ITS1 ITS0 [15:0] ITSy(y = 0..15) WRITE as : ‘0’ is no effect ‘1’ is sets the interrupt type bit READ as : ‘0’ is indicates for LOW or HIGH level ‘1’...

  • Page 160: Gpio Interrupt Polarity Clear Register(Gpiox_ Intpolclr) (X=A

    IPS15 IPS14 IPS13 IPS12 IPS11 IPS10 IPS9 IPS8 IPS7 IPS6 IPS5 IPS4 IPS3 IPS2 IPS1 IPS0 [15:0] IPSy(y = 0..15) WRITE as : ‘0’ is no effect ‘1’ is sets the interrupt polarity bit READ as : ‘0’ is indicates for LOW level or falling edge ‘1’...

  • Page 161: Gpio Interrupt Status/Clear Register(Gpio_ Intstatus/Intclear) (X=A

    GPIO Interrupt Status/Interrupt Clear Register(GPIO_ INTSTATUS/ INTCLEAR) (x=A..D) Address offset: 0x0038 Reset value: 0x---- ISC15 ISC14 ISC13 ISC12 ISC11 ISC10 ISC9 ISC8 ISC7 ISC6 ISC5 ISC4 ISC3 ISC2 ISC1 ISC0 [15:0] ISCy(y = 0..15) WRITE as : ‘0’ is no effect ‘1’...

  • Page 162: Gpio Upper Byte Masked Access Register(Gpiox_ Ub_Masked) (X=A

    GPIO Upper Byte Masked Access Register(GPIOx_ UB_MASKED) (x=A..D) Address offset: 0x0800-0x0FC Reset value: 0x---- Higher eight bits masked access [15:8] Data for higher byte access, with bits[9:2] of address value used as enable bit mask for each bit [7:0] Not used 162 / 399 W7500x Reference Manual Version1.1.0...

  • Page 163: Register Map

    18.5 Register map The following Table 13 summarizes the GPIO registers. Table 13 GPIO register map and reset values 163 / 399 W7500x Reference Manual Version1.1.0...

  • Page 164: Direct Memory Access Controller (Dma)

    Direct memory access controller (DMA) 19.1 Introduction Direct memory access (DMA) is used in order to provide high-speed data transfer between peripherals and memory as well as memory to memory. Data can be quickly moved by DMA without any CPU actions. This keeps CPU resources free for other operations. The DMA controller has up to 6 channels in total, each dedicated to managing memory access requests from one or more peripherals.

  • Page 165: Dma Request Mapping

    DMA request mapping The hardware requests from the peripherals (UART0, UART1, SSP0, SSP1) are simply connected to the DMA. Refer to Table 17 which lists the DMA requests for each channel. Table 14 Summary of the DMA requests for each channel Channel 1 Channel 2 Channel 3...
  • Page 166 Ping-pong  See ARM micro DMA (PL230) documentation for additional cycle types. For all cycle types, the controller arbitrates after 2 DMA transfers. If a low-priority channel is set to a large 2 value then it prevents all other channels from performing a DMA transfer until the low-priority DMA transfer completes.
  • Page 167 In this mode, the controller can be configured to use either the primary or the alternate channel control data structure. After the channel is enabled and the controller receives a request for this channel, the flow for the auto-request cycle is as below: The controller performs 2 transfers.

  • Page 168: Registers (Base Address : 0X4100_4000)

    Figure 18. DMA ping pong cycle 19.4 Registers (Base address : 0x4100_4000) DMA status register (DMA_STATUS) Address offset : 0x000 168 / 399 W7500x Reference Manual Version1.1.0...

  • Page 169: Dma Configuration Register (Dma_Cfg)

    Reset value : 0x0005_0000 STATE ENABLE [0] ENABLE – Enable status of the controller This bit is read only register to check enable status of DMA controller 0 : controller is disabled 1 : controller is enabled [7:4] STATE – Current state of the control state machine. These bits are read only register to check current state of controller.

  • Page 170: Dma Control Data Base Pointer Register (Dma_Ctrl_Base_Ptr)

    [0] ENABLE – Enable for the controller This bit is write only register to enable of DMA controller 0 : disable the controller 1 : enable the controller [7:5] PROT_CTRL – Set the AHB-Lite protection by controlling the HPROT[3:1] signal levels These bits are write only register to set HPROT[3:1] signal as follows [7] : controls HPROT[3] to indicate if a cacheable access is occurring.

  • Page 171: Dma Channel Wait On Request Status Register (Dma_Waitonreq_Status)

    [31:0] ALT_CTRL_BASE_PTR : Base address of the alternate data structure This read only register returns the base address of the alternate data structure. DMA channel wait on request status register (DMA_WAITONREQ_STATUS) Address offset : 0x010 Reset value : 0x0000_0000 DMA_WAITONREQ[5:0] [Channel-1] DMA_WAITONREQ –...

  • Page 172: Dma Channel Useburst Set Register (Dma_Chnl_Useburst_Set)

    1 : creates a DMA request for [Channel -1] DMA channel useburst set register (DMA_CHNL_USEBURST_SET) Address offset : 0x018 Reset value : 0x0000_0000 CHNL_USEBURST_SET[5:0] [Channel-1] CHNL_USEBURST_SET – Returns the useburst status, or disable dma_sreq[Channel-1] form generating DMA requests. This read/write register disables the single request dma_sreq[Channel-1] input from generating requests, and therefore only the request, dma_req[Channel-1],generates requests.

  • Page 173: Dma Channel Request Mask Set Register (Dma_Chnl_Req_Mask_Set)

    CHNL_USEBURST_CLR[5:0] [Channel-1] CHNL_USEBURST_CLR appropriate enable dma_sreq[Channel-1] to generate requests. This Write register enables dma_sreq[Channel-1] to generate requests. 0 – No effect. User the CHNL_USEBURST_SET register to disable dma_sreq[Channel-1] from generating requests. 1 – Enable dma_sreq[Channel-1] to generate DMA requests. DMA channel request mask set register (DMA_CHNL_REQ_MASK_SET) Address offset : 0x020 Reset value : 0x0000_0000...

  • Page 174: Dma Channel Request Mask Clear Register (Dma_Chnl_Req_Mask_Clr)

    DMA channel request mask clear register (DMA_CHNL_REQ_MASK_CLR) Address offset : 0x024 Reset value : - CHNL_REQ_MASK_CLR[5:0] [Channel-1] CHNL_REQ_MASK_CLR – Set the appropriate bit to enable DMA requests for the channel corresponding to dma_req[Channel-1] and dma_sreq[Channel-1] This write only register enables a HIGH on dma_req[Channel-1], or dma_sreq[Channel- 0 : No effect.

  • Page 175: Dma Channel Enable Clear Register (Dma_Chnl_Enable_Clr)

    1 – Channel [Channel-1] is enabled Write as : 0 – No effect. Use the CHNL_ENABLE_CLR register to disable a channel. 1 – Enables channels [Channel-1] DMA channel enable clear register (DMA_CHNL_ENABLE_CLR) Address offset : 0x02c Reset value : - CHNL_ENABLE_CLR[5:0] [Channel-1] CHNL_ENABLE_CLR –...

  • Page 176: Dma Channel Primary-Alternate Clear Register (Dma_Chnl_Pri_Alt

    This read/write register configure a DMA channel to use the alternate data structure. Reading the register returns the status of which data structure is in use for the corresponding DMA channel. Read as : 0 – DMA Channel [Channel-1] is using the primary data structure. 1 –...

  • Page 177: Dma Channel Priority Clear Register (Dma_Chnl_Priority_Clr)

    CHNL_PRIORITY_SET [5:0] [Channel-1] CHNL_PRIORITY_SET - Returns the channel priority mask status, or set the channel priority to high. This read/write register configure a DMA channel to use the high priority level. Reading the register returns the status of channel priority mask Read as : 0 –...
  • Page 178 ERR_CLR [0] ERR_CLR – Returns the status of DMA_ERR, or set the signal LOW. This read/write register returns the status of DMA_ERR, and enables set DMA_ERR LOW. Read as : 0 : DMA_ERR is LOW 1 : DMA_ERR is HIGH Write as : 0 : No effect, status of DMA_ERR is unchanged.

  • Page 179: Register Map

    19.5 Register map The following Table 15 summarizes the DMA registers. Table 15 DMA register map and reset values Offset Register STATE DMA_STATUS 0x000 reset value DMA_CFG PROT_CTRL 0x004 reset value CTRL_BASE_PTR DMA_CTRL_BASE_PTR 0x008 reset value ALT_CTRL_BASE_PTR DMA_ALT_CTRL_BASE_PTR 0x00C reset value DMA_WAITONREQ DMA_WAITONREQ_STATUS 0x010...

  • Page 180: Analog-To-Digital Converter (Adc)

    Analog-to-digital converter (ADC) 20.1 Introduction ADC is a 12bit analog-to-digital converter. It has up to 9 multiplexed channels allowing it to measure signals from 8 externals and 1 internal source. ADC of various channels can be performed in single mode. The result of the ADC is stored in 12 bit register.

  • Page 181: Functional Description

    20.3 Functional description Figure 19 shows the ADC block diagram. MASK INT CTRL INTCLR RSTn SMPSEL ADCCLK START Controller (Registers) APB IF CHSEL[3:0] Digital&SAR Logic DATA[11:0] ADC_IN[9:0] 9-to-1 Figure 19. ADC block diagram Operation ADC with non-interrupt Figure 20 shows the flowchart of ADC operation with non-interrupt. ADC can be used as below: 1.
  • Page 182 START ADC Power On (PWD = 0) Select Channel (ADC_CHSEL) ADC Start (ADC_SRT) CHECK INT bit (INT == 1 ??) Read ADC conversion data (ADC_DATA) ADC again? ADC Power off (PWD = 1) Figure 20. The ADC operation flowchart with non-interrupt 182 / 399 W7500x Reference Manual Version1.1.0...

  • Page 183: Operation Adc With Interrupt

    Operation ADC with interrupt Figure 21 shows the flowchart of ADC operation with interrupt. Operation is almost the same as the non-interrupt mode except checking INT register bit to know when enabling interrupt mask bit and conversion is completed. START ADC Power On (PWD = 0) Interrupt MASK enable...

  • Page 184: Adc Channel Select Register (Adc_Chsel)

    SMPSEL [0] SMPSEL – Sampling mode select This bit written by S/W to select sampling mode 0 : Abnormal mode 1 : Normal mode [1] PWD – Power down This bit set and cleared by S/W to enable/disable power down mode O : Active 1 : Power down ADC channel select register (ADC_CHSEL)

  • Page 185: Adc Start Register (Adc_Start)

    1000 ~ 1000 : no select 1111 : LDO output(1.5V) select ADC start register (ADC_START) Address offset : 0x008 Reset value : 0x0000_0000 ADC_SRT [0] ADC_SRT – ADC Start bit This bit set by S/W to start ADC for conversion. This bit is write-only. 0 : ready to start 1 : start ADC for conversion (This bit clear automatically after conversion) ADC conversion data register (ADC_DATA)

  • Page 186: Adc Interrupt Clear Register (Adc_Intclr)

    MASK [0] DONE – Interrupt bit This bit indicates that conversion is done or not. This bit is set after conversion is done and this bit is cleared by set of Interrupt clear bit. This bit is read-only. [1] MASK – Interrupt mask signal. This bit is interrupt mask bit of ADC.

  • Page 187: Register Map

    20.5 Register map The following Table 16 summarizes the ADC registers. Table 16 ADC register map and reset values Offset Register ADC_CTR 0x000 reset value ADC_CHSEL CHSEL 0x004 reset value ADC_START 0x008 reset value DATA ADC_DATA 0x00C reset value ADC_INT 0x010 reset value ADC_INTCLR...

  • Page 188: Pulse-Width Modulation (Pwm)

    Pulse-Width Modulation (PWM) 21.1 Introduction The PWM consists a 8-channel 32-bit Timer/Counter driven by a programmable prescaler. The function of the PWM is based on the basic Timer. Each timer and counter runs independently. The PWM can be used to control the width of the pulse, formally the pulse duration, to generate output waveform or to count the counter triggered by external input.

  • Page 189: Functional Description

    Figure 22 PWM block diagram 21.3 Functional description Timer/Counter control The PWM has Start/Stop register. It controls start or stop of the Timer/Counter. If you set this register, the Timer/Counter starts to run. If you reset this register, the Timer/Counter stops immediately.
  • Page 190 Figure 23 Periodic mode In one-shot mode, the Timer /Counter reset to the initial value and then stops when the Timer/Counter reaches the value of limit register. Figure 24 shows one-shot mode timing diagram. PWMCLK Prescale Counter Timer/Counter Overflow Interrupt Figure 24 one-shot mode Counting mode The Timer/Counter has two counting mode: Up-count and Down-count mode.
  • Page 191 The Timer/Counter can run in timer mode or counter mode. In timer mode, the Timer/Counter is counted by PWMCLK after Prescale counter is overflowed. If prescale is set by 0, the Timer/Counter counts every PWMCLK period. In counter mode, the Timer/Counter is counted by external input signal.
  • Page 192 External Input Start/Stop Register Rising edge detect Falling edge detect Timer/Counter Figure 29 Counter mode with rising and falling edge Prescaler description The PWM has 6-bit prescale counter(PC) and the prescaler can divide the Timer/Counter clock frequency. Users can control it by Prescale Register(PR). Figure 30 and Figure 31 shows some examples of the Timer/Counter timing with prescale register is 2, match register is 2, limit register is 12, timer mode, periodic mode, up-count mode, and no interrupt clear.

  • Page 193: Pwm Mode

    PWMCLK Start/Stop Register Prescale Counter Timer/Counter Prescale Counter Overflow Overflow Interrupt Interrupt Register[2:0] Figure 31 Timer/Counter timing diagram with overflow interrupt PWM mode Pulse Width Modulation mode generates a waveform with a period determined by the value of limit register and a duty cycle determined by the value of the match register. The PWM output becomes always 1 when the Timer/Counter starts to count.

  • Page 194: Interrupt

    PWMCLK Start/Stop Register Timer/Counter PWM output Match Interrupt Match register Figure 32 The PWM output up to match register PWMCLK Start/Stop Register Timer/Counter PWM output Overflow Interrupt Limit register Figure 33 The PWM output up to limit register If match register is set as 0, the PWM output will be 1 while the Timer/Counter is 0. If the match register is bigger than the limit register, the PWM output is always 1.

  • Page 195: Dead Zone Generation

    If interrupt occurs, corresponded bit of Channel-x interrupt register(CHn_IR) bit is set and PWM channel-n interrupt signal is generated. All CHn_IR is cleared by channel-n interrupt clear register(CHn_ICR) and then PWM channel-n interrupt signal is cleared. Dead zone generation Each PWM channel can output two complementary signals with dead zone time and it can be enabled by Channel-n Dead Zone Enable Register(CHn_DZER).

  • Page 196: Capture Event

    PWMCLK Start/Stop Register Dead zone Counter Timer/Counter output Inverted PWM output Dead zone counter register Match register Figure 35 PWM waveform with dead zone counter Capture event Each PWM channel can capture its Timer/Counter value when an external input signal changes. Any channel could use any method of rising or falling edges.
  • Page 197 Figure 37 shows, also, capture event timing diagram with interrupt clear. The second capture is saved at the second rising edge detection because there is interrupt clear. External Input Rising edge detect Timer/Counter Capture Interrupt Capture Interrupt clear Figure 37 Capture event with interrupt clear 197 / 399 W7500x Reference Manual Version1.1.0...

  • Page 198: How To Set The Pwm

    How to set the PWM Figure 38 shows the PWM setting flow step by step. Set the registers: CHn_PR, CHn_MR, CHn_LR, CHn_UDMR, CHn_PDMR Timer Counter Timer or Counter mode? CHn_TCMR[1:0] = CHn_TCMR[1:0] = 01 / Rising edge 00 / Timer mode 10 / Falling edge 11 / both edge CHn_PEEER[1:0] =...

  • Page 199: Channel-0 Interrupt Enable Register(Pwmch0Ier)

    [0] MI – Match Interrupt This bit is set by hardware and cleared by interrupt clear register. 0 : Match interrupt does not occur. 1 : Match interrupt occurs. [1] OI – Overflow Interrupt This bit is set by hardware and cleared by interrupt clear register. 0 : Overflow interrupt does not occur.

  • Page 200: Channel-0 Interrupt Clear Register(Pwmch0Icr)

    Channel-0 interrupt clear register(PWMCH0ICR) Base address : 0x4000_5000 Address offset : 0x08 This bit is set by software, cleared by hardware when a capture interrupt becomes 0. [0] MIC – Match Interrupt 0 : No action. 1 : Match interrupt is cleared. [1] OIC –...

  • Page 201: Channel-0 Prescale Counter Register (Pwmch0Pcr)

    Channel-0 Prescale Counter Register (PWMCH0PCR) Base address : 0x4000_5000 Address offset : 0x10 Reset value : 0x0000_0000 [5:0] PC – Prescale Counter register Prescale Counter register. These registers hold the current values of prescale counter(PC). The PC is incremented to the value stored in PR. When the PC is reached to PR, the TC is incremented and the PC is reset as 0.

  • Page 202: Channel-0 Limit Register (Pwmch0Lr)

    [31:0] MR – Match Register Match register. The MR can generate a match interrupt and PWM output waveform becomes 0 when the TC is reached to the MR. Match register should be smaller than limit register(LR). If not, match interrupt is not occurred and PWM output waveform is always 1.

  • Page 203: Channel-0 Timer/Counter Mode Register (Pwmch0Tcmr)

    1 : TC runs down count. Channel-0 Timer/Counter Mode Register (PWMCH0TCMR) Base address : 0x4000_5000 Address offset : 0x24 Reset value : 0x0000_0000 [1:0] TCM – Timer/Counter mode 00 : Timer mode. 01 : Counter mode with counting driven by rising edge external input . 10 : Counter mode with counting driven by falling edge external input.

  • Page 204: Channel-0 Capture Mode Register (Pwmch0Cmr)

    Channel-0 Capture Mode Register (PWMCH0CMR) Base address : 0x4000_5000 Address offset : 0x2C Reset value : 0x0000_0000 [0] CM – Capture mode 0 : Timer/Counter is captured when external input signal is rising edge. 1 : Timer/Counter is captured when external input signal is falling edge. Channel-0 Capture Register (PWMCH0CR) Base address : 0x4000_5000 Address offset : 0x30...

  • Page 205: Channel-0 Dead Zone Enable Register (Pwmch0Dzer)

    [0] PDM – Periodic Mode 0 : Periodic mode. When the TC is reached to the LR, the TC returns to 0 and then continues counting periodically. 1 : One-shot mode. When the TC is reached to the LR, the TC returns to 0 and then stops counting.

  • Page 206: Register Map

    [9:0] DZC – Dead Zone Counter value Dead zone generation counter value register. If the DZE bit in DZER is 1, dead zone counter counts to this value and during this time, the two PWM output waveforms are all 0. 21.5 Register map The following Table 17 summarizes the PWM Channel-0 registers.

  • Page 207: Table 17 Pwm Channel 0 Register Map And Reset Values

    Table 17 PWM channel 0 register map and reset values Offset Register 비고 PWMCH0IR Channel-0 interrupt register 0x00 reset value PWMCH0IER Channel-0 interrupt enable register 0x04 reset value PWMCH0ICR Channel-0 interrupt clear register 0x08 reset value Write only register PWMCH0TCR Channel-0 Timer/Counter Register 0x0C reset value...

  • Page 208: Pwm Channel-1 Registers (Base Address : 0X4000_5100)

    21.6 PWM Channel-1 Registers (Base address : 0x4000_5100) Channel-1 interrupt register(PWMCH1IR) Base address : 0x4000_5100 Address offset : 0x00 Reset value : 0x0000_0000 [0] MI – Match Interrupt This bit is set by hardware and cleared by interrupt clear register. O : Match interrupt does not occur.

  • Page 209: Channel-1 Interrupt Clear Register(Pwmch1Icr)

    [0] MIE – Match Interrupt Enabled. O : Match interrupt is not enabled. 1 : Match interrupt is enabled. [1] OIE – Overflow Interrupt Enable. O : Overflow interrupt is not enabled. 1 : Overflow interrupt is enabled. [2] CIE – Capture Interrupt Enable. O : Capture interrupt is not enabled.

  • Page 210: Channel-1 Prescale Counter Register (Pwmch1Pcr)

    [31:0] TCR – Timer/Counter register Timer/Counter register. These register hold the current values of the Timer/Counter(TC). The TC is incremented every PR cycles. When the TC is reached to value of match register, the match interrupt is occurred and PWM output waveform becomes 0.

  • Page 211: Channel-1 Match Register (Pwmch1Mr)

    [5: 0] PR – Prescale Register Prescale register. The PC is incremented when the PC is reached to the PR. Channel-1 Match Register (PWMCH1MR) Base address : 0x4000_5100 Address offset : 0x18 Reset value : 0x0000_0000 [31:0] MR – Match Register Match register.

  • Page 212: Channel-1 Up-Down Mode Register (Pwmch1Udmr)

    Channel-1 Up-Down Mode Register (PWMCH1UDMR) Base address : 0x4000_5100 Address offset : 0x20 Reset value : 0x0000_0000 [0] UDM – Up-Down mode 0 : TC runs up count. 1 : TC runs down count. Channel-1 Timer/Counter Mode Register (PWMCH1TCMR) Base address : 0x4000_5100 Address offset : 0x24 Reset value : 0x0000_0000 [1:0] TCM –...

  • Page 213: Channel-1 Pwm Output Enable And External Input Enable Register (Pwmch1Peeer)

    Channel-1 PWM output Enable and External input Enable Register (PWMCH1PEEER) Base address : 0x4000_5100 Address offset : 0x28 Reset value : 0x0000_0000 PEEE [1:0] PEEE – PWM output Enable and External input Enable 00 : PWM output is disable and external input is disable. 01 : PWM output is disable and external input is enable.

  • Page 214: Channel-1 Periodic Mode Register (Pwmch1Pdmr)

    Reset value : 0x0000_0000 [31:0] CR – Capture Register Capture register. The CR is loaded with the value of the TC when external input signal is triggered. Channel-1 Periodic Mode Register (PWMCH1PDMR) Base address : 0x4000_5100 Address offset : 0x34 Reset value : 0x0000_0000 [0] PDM –...

  • Page 215: Channel-1 Dead Zone Counter Register (Pwmch1Dzcr)

    [0] DZE – Dead Zone Enable 0 : Dead zone generation is disabled. 1 : Dead zone generation is enabled. Channel-1 Dead Zone Counter Register (PWMCH1DZCR) Base address : 0x4000_5100 Address offset : 0x3C Reset value : 0x0000_0000 [9:0] DZC – Dead Zone Counter value Dead zone generation counter value register.

  • Page 216: Register Map

    21.7 Register map The following Table 18 summarizes the PWM Channel-1 registers. Table 18 PWM channel 1 register map and reset values Offset Register 비고 PWMCH1IR Channel-1 interrupt register 0x00 reset value PWMCH1IER Channel-1 interrupt enable register 0x04 reset value PWMCH1ICR Channel-1 interrupt clear register 0x08...

  • Page 217: Pwm Channel-2 Registers (Base Address : 0X4000_5200)

    21.8 PWM Channel-2 Registers (Base address : 0x4000_5200) Channel-2 interrupt register(PWMCH2IR) Base address : 0x4000_5200 Address offset : 0x00 Reset value : 0x0000_0000 [0] MI – Match Interrupt This bit is set by hardware and cleared by interrupt clear register. O : Match interrupt does not occur.

  • Page 218: Channel-2 Interrupt Clear Register(Pwmch2Icr)

    [0] MIE – Match Interrupt Enabled. O : Match interrupt is not enabled. 1 : Match interrupt is enabled. [1] OIE – Overflow Interrupt Enable. O : Overflow interrupt is not enabled. 1 : Overflow interrupt is enabled. [2] CIE – Capture Interrupt Enable. O : Capture interrupt is not enabled.

  • Page 219: Channel-2 Prescale Counter Register (Pwmch2Pcr)

    [31:0] TCR – Timer/Counter register Timer/Counter register. These register hold the current values of the Timer/Counter(TC). The TC is incremented every PR cycles. When the TC is reached to value of match register, the match interrupt is occurred and PWM output waveform becomes 0.

  • Page 220: Channel-2 Match Register (Pwmch2Mr)

    [5: 0] PR – Prescale Register Prescale register. The PC is incremented when the PC is reached to the PR. Channel-2 Match Register (PWMCH2MR) Base address : 0x4000_5200 Address offset : 0x18 Reset value : 0x0000_0000 [31:0] MR – Match Register Match register.

  • Page 221: Channel-2 Timer/Counter Mode Register (Pwmch2Tcmr)

    Address offset : 0x20 Reset value : 0x0000_0000 [0] UDM – Up-Down mode 0 : TC runs up count. 1 : TC runs down count. Channel-2 Timer/Counter Mode Register (PWMCH2TCMR) Base address : 0x4000_5200 Address offset : 0x24 Reset value : 0x0000_0000 [1:0] TCM –...

  • Page 222: Channel-2 Capture Mode Register (Pwmch2Cmr)

    PEEE [1:0] PEEE – PWM output Enable and External input Enable 00 : PWM output is disable and external input is disable. 01 : PWM output is disable and external input is enable. 10 : PWM output is enable and external input is disable. Channel-2 Capture Mode Register (PWMCH2CMR) Base address : 0x4000_5200 Address offset : 0x2C...

  • Page 223: Channel-2 Periodic Mode Register (Pwmch2Pdmr)

    Capture register. The CR is loaded with the value of the TC when external input signal is triggered. Channel-2 Periodic Mode Register (PWMCH2PDMR) Base address : 0x4000_5200 Address offset : 0x34 Reset value : 0x0000_0000 [0] PDM – Periodic Mode 0 : Periodic mode.

  • Page 224: Channel-2 Dead Zone Counter Register (Pwmch2Dzcr)

    Channel-2 Dead Zone Counter Register (PWMCH2DZCR) Base address : 0x4000_5200 Address offset : 0x3C Reset value : 0x0000_0000 [9:0] DZC – Dead Zone Counter value Dead zone generation counter value register. If the DZE bit in DZER is 1, dead zone counter counts to this value and during this time, the two PWM output waveforms are all 0.

  • Page 225: Register Map

    21.9 Register map The following Table 19 summarizes the PWM Channel-2 registers. Table 19 PWM channel 2 register map and reset values Offset Register 비고 PWMCH2IR Channel-2 interrupt register 0x00 reset value PWMCH2IER Channel-2 interrupt enable register 0x04 reset value PWMCH2ICR Channel-2 interrupt clear register 0x08...

  • Page 226: Pwm Channel-3 Registers (Base Address : 0X4000_5300)

    21.10 PWM Channel-3 Registers (Base address : 0x4000_5300) Channel-3 interrupt register(PWMCH3IR) Base address : 0x4000_5300 Address offset : 0x00 Reset value : 0x0000_0000 [0] MI – Match Interrupt This bit is set by hardware and cleared by interrupt clear register. O : Match interrupt does not occur.

  • Page 227: Channel-3 Interrupt Clear Register(Pwmch3Icr)

    [0] MIE – Match Interrupt Enabled. O : Match interrupt is not enabled. 1 : Match interrupt is enabled. [1] OIE – Overflow Interrupt Enable. O : Overflow interrupt is not enabled. 1 : Overflow interrupt is enabled. [2] CIE – Capture Interrupt Enable. O : Capture interrupt is not enabled.

  • Page 228: Channel-3 Prescale Counter Register (Pwmch3Pcr)

    [31:0] TCR – Timer/Counter register Timer/Counter register. These register hold the current values of the Timer/Counter(TC). The TC is incremented every PR cycles. When the TC is reached to value of match register, the match interrupt is occurred and PWM output waveform becomes 0.

  • Page 229: Channel-3 Match Register (Pwmch3Mr)

    [5: 0] PR – Prescale Register Prescale register. The PC is incremented when the PC is reached to the PR. Channel-3 Match Register (PWMCH3MR) Base address : 0x4000_5300 Address offset : 0x18 Reset value : 0x0000_0000 [31:0] MR – Match Register Match register.

  • Page 230: Channel-3 Up-Down Mode Register (Pwmch3Udmr)

    Channel-3 Up-Down Mode Register (PWMCH3UDMR) Base address : 0x4000_5300 Address offset : 0x20 Reset value : 0x0000_0000 [0] UDM – Up-Down mode 0 : TC runs up count. 1 : TC runs down count. Channel-3 Timer/Counter Mode Register (PWMCH3TCMR) Base address : 0x4000_5300 Address offset : 0x24 Reset value : 0x0000_0000 [1:0] TCM –...

  • Page 231: Channel-3 Pwm Output Enable And External Input Enable Register (Pwmch3Peeer)

    Channel-3 PWM output Enable and External input Enable Register (PWMCH3PEEER) Base address : 0x4000_5300 Address offset : 0x28 Reset value : 0x0000_0000 PEEE [1:0] PEEE – PWM output Enable and External input Enable 00 : PWM output is disable and external input is disable. 01 : PWM output is disable and external input is enable.

  • Page 232: Channel-3 Periodic Mode Register (Pwmch3Pdmr)

    Reset value : 0x0000_0000 [31:0] CR – Capture Register Capture register. The CR is loaded with the value of the TC when external input signal is triggered. Channel-3 Periodic Mode Register (PWMCH3PDMR) Base address : 0x4000_5300 Address offset : 0x34 Reset value : 0x0000_0000 [0] PDM –...

  • Page 233: Channel-3 Dead Zone Counter Register (Pwmch3Dzcr)

    [0] DZE – Dead Zone Enable 0 : Dead zone generation is disabled. 1 : Dead zone generation is enabled. Channel-3 Dead Zone Counter Register (PWMCH3DZCR) Base address : 0x4000_5300 Address offset : 0x3C Reset value : 0x0000_0000 [9:0] DZC – Dead Zone Counter value Dead zone generation counter value register.

  • Page 234: Register Map

    21.11 Register map The following Table 20 summarizes the PWM Channel-3 registers. Table 20 PWM channel 3 register map and reset values Offset Register 비고 PWMCH3IR Channel-3 interrupt register 0x00 reset value PWMCH3IER Channel-3 interrupt enable register 0x04 reset value PWMCH3ICR Channel-3 interrupt clear register 0x08...

  • Page 235: Pwm Channel-4 Registers (Base Address : 0X4000_5400)

    21.12 PWM Channel-4 Registers (Base address : 0x4000_5400) Channel-4 interrupt register(PWMCH4IR) Base address : 0x4000_5400 Address offset : 0x00 Reset value : 0x0000_0000 [0] MI – Match Interrupt This bit is set by hardware and cleared by interrupt clear register. O : Match interrupt does not occur.

  • Page 236: Channel-4 Interrupt Clear Register(Pwmch4Icr)

    [0] MIE – Match Interrupt Enabled. O : Match interrupt is not enabled. 1 : Match interrupt is enabled. [1] OIE – Overflow Interrupt Enable. O : Overflow interrupt is not enabled. 1 : Overflow interrupt is enabled. [2] CIE – Capture Interrupt Enable. O : Capture interrupt is not enabled.

  • Page 237: Channel-4 Prescale Counter Register (Pwmch4Pcr)

    [31:0] TCR – Timer/Counter register Timer/Counter register. These register hold the current values of the Timer/Counter(TC). The TC is incremented every PR cycles. When the TC is reached to value of match register, the match interrupt is occurred and PWM output waveform becomes 0.

  • Page 238: Channel-4 Match Register (Pwmch4Mr)

    [5: 0] PR – Prescale Register Prescale register. The PC is incremented when the PC is reached to the PR. Channel-4 Match Register (PWMCH4MR) Base address : 0x4000_5400 Address offset : 0x18 Reset value : 0x0000_0000 [31:0] MR – Match Register Match register.

  • Page 239: Channel-4 Timer/Counter Mode Register (Pwmch4Tcmr)

    Reset value : 0x0000_0000 [0] UDM – Up-Down mode 0 : TC runs up count. 1 : TC runs down count. Channel-4 Timer/Counter Mode Register (PWMCH4TCMR) Base address : 0x4000_5400 Address offset : 0x24 Reset value : 0x0000_0000 [1:0] TCM – Timer/Counter mode 00 : Timer mode.

  • Page 240: Channel-4 Capture Mode Register (Pwmch4Cmr)

    PEEE [1:0] PEEE – PWM output Enable and External input Enable 00 : PWM output is disable and external input is disable. 01 : PWM output is disable and external input is enable. 10 : PWM output is enable and external input is disable. Channel-4 Capture Mode Register (PWMCH4CMR) Base address : 0x4000_5400 Address offset : 0x2C...

  • Page 241: Channel-4 Periodic Mode Register (Pwmch4Pdmr)

    Capture register. The CR is loaded with the value of the TC when external input signal is triggered. Channel-4 Periodic Mode Register (PWMCH4PDMR) Base address : 0x4000_5400 Address offset : 0x34 Reset value : 0x0000_0000 [0] PDM – Periodic Mode 0 : Periodic mode.

  • Page 242: Channel-4 Dead Zone Counter Register (Pwmch4Dzcr)

    Channel-4 Dead Zone Counter Register (PWMCH4DZCR) Base address : 0x4000_5400 Address offset : 0x3C Reset value : 0x0000_0000 [9:0] DZC – Dead Zone Counter value Dead zone generation counter value register. If the DZE bit in DZER is 1, dead zone counter counts to this value and during this time, the two PWM output waveforms are all 0.

  • Page 243: Register Map

    21.13 Register map The following Table 21 summarizes the PWM Channel-4 registers. Table 21 PWM channel 4 register map and reset values Offset Register 비고 PWMCH4IR Channel-4 interrupt register 0x00 reset value PWMCH4IER Channel-4 interrupt enable register 0x04 reset value PWMCH4ICR Channel-4 interrupt clear register 0x08...

  • Page 244: Pwm Channel-5 Registers (Base Address : 0X4000_5500)

    21.14 PWM Channel-5 Registers (Base address : 0x4000_5500) Channel-5 interrupt register(PWMCH5IR) Base address : 0x4000_5500 Address offset : 0x00 Reset value : 0x0000_0000 [0] MI – Match Interrupt This bit is set by hardware and cleared by interrupt clear register. O : Match interrupt does not occur.

  • Page 245: Channel-5 Interrupt Clear Register(Pwmch5Icr)

    [0] MIE – Match Interrupt Enabled. O : Match interrupt is not enabled. 1 : Match interrupt is enabled. [1] OIE – Overflow Interrupt Enable. O : Overflow interrupt is not enabled. 1 : Overflow interrupt is enabled. [2] CIE – Capture Interrupt Enable. O : Capture interrupt is not enabled.

  • Page 246: Channel-5 Prescale Counter Register (Pwmch5Pcr)

    [31:0] TCR – Timer/Counter register Timer/Counter register. These register hold the current values of the Timer/Counter(TC). The TC is incremented every PR cycles. When the TC is reached to value of match register, the match interrupt is occurred and PWM output waveform becomes 0.

  • Page 247: Channel-5 Match Register (Pwmch5Mr)

    [5: 0] PR – Prescale Register Prescale register. The PC is incremented when the PC is reached to the PR. Channel-5 Match Register (PWMCH5MR) Base address : 0x4000_5500 Address offset : 0x18 Reset value : 0x0000_0000 [31:0] MR – Match Register Match register.

  • Page 248: Channel-5 Timer/Counter Mode Register (Pwmch5Tcmr)

    Address offset : 0x20 Reset value : 0x0000_0000 [0] UDM – Up-Down mode 0 : TC runs up count. 1 : TC runs down count. Channel-5 Timer/Counter Mode Register (PWMCH5TCMR) Base address : 0x4000_5500 Address offset : 0x24 Reset value : 0x0000_0000 [1:0] TCM –...

  • Page 249: Channel-5 Capture Mode Register (Pwmch5Cmr)

    PEEE [1:0] PEEE – PWM output Enable and External input Enable 00 : PWM output is disable and external input is disable. 01 : PWM output is disable and external input is enable. 10 : PWM output is enable and external input is disable. Channel-5 Capture Mode Register (PWMCH5CMR) Base address : 0x4000_5500 Address offset : 0x2C...

  • Page 250: Channel-5 Periodic Mode Register (Pwmch5Pdmr)

    [31:0] CR – Capture Register Capture register. The CR is loaded with the value of the TC when external input signal is triggered. Channel-5 Periodic Mode Register (PWMCH5PDMR) Base address : 0x4000_5500 Address offset : 0x34 Reset value : 0x0000_0000 [0] PDM –...

  • Page 251: Channel-5 Dead Zone Counter Register (Pwmch5Dzcr)

    Channel-5 Dead Zone Counter Register (PWMCH5DZCR) Base address : 0x4000_5500 Address offset : 0x3C Reset value : 0x0000_0000 [9:0] DZC – Dead Zone Counter value Dead zone generation counter value register. If the DZE bit in DZER is 1, dead zone counter counts to this value and during this time, the two PWM output waveforms are all 0.

  • Page 252: Register Map

    21.15 Register map The following Table 22 summarizes the PWM Channel-5 registers. Table 22 PWM channel 5 register map and reset values Offset Register 비고 PWMCH5IR Channel-5 interrupt register 0x00 reset value PWMCH5IER Channel-5 interrupt enable register 0x04 reset value PWMCH5ICR Channel-5 interrupt clear register 0x08...

  • Page 253: Pwm Channel-6 Registers (Base Address : 0X4000_5600)

    21.16 PWM Channel-6 Registers (Base address : 0x4000_5600) Channel-6 interrupt register(PWMCH6IR) Base address : 0x4000_5600 Address offset : 0x00 Reset value : 0x0000_0000 [0] MI – Match Interrupt This bit is set by hardware and cleared by interrupt clear register. O : Match interrupt does not occur.

  • Page 254: Channel-6 Interrupt Clear Register(Pwmch6Icr)

    [0] MIE – Match Interrupt Enabled. O : Match interrupt is not enabled. 1 : Match interrupt is enabled. [1] OIE – Overflow Interrupt Enable. O : Overflow interrupt is not enabled. 1 : Overflow interrupt is enabled. [2] CIE – Capture Interrupt Enable. O : Capture interrupt is not enabled.

  • Page 255: Channel-6 Prescale Counter Register (Pwmch6Pcr)

    [31:0] TCR – Timer/Counter register Timer/Counter register. These register hold the current values of the Timer/Counter(TC). The TC is incremented every PR cycles. When the TC is reached to value of match register, the match interrupt is occurred and PWM output waveform becomes 0.

  • Page 256: Channel-6 Match Register (Pwmch6Mr)

    [5:0] PR – Prescale Register Prescale register. The PC is incremented when the PC is reached to the PR. Channel-6 Match Register (PWMCH6MR) Base address : 0x4000_5600 Address offset : 0x18 Reset value : 0x0000_0000 [31:0] MR – Match Register Match register.

  • Page 257: Channel-6 Up-Down Mode Register (Pwmch6Udmr)

    Channel-6 Up-Down Mode Register (PWMCH6UDMR) Base address : 0x4000_5600 Address offset : 0x20 Reset value : 0x0000_0000 [0] UDM – Up-Down mode 0 : TC runs up count. 1 : TC runs down count. Channel-6 Timer/Counter Mode Register (PWMCH6TCMR) Base address : 0x4000_5600 Address offset : 0x24 Reset value : 0x0000_0000 [1:0] TCM –...

  • Page 258: Channel-6 Pwm Output Enable And External Input Enable Register (Pwmch6Peeer)

    Channel-6 PWM output Enable and External input Enable Register (PWMCH6PEEER) Base address : 0x4000_5600 Address offset : 0x28 Reset value : 0x0000_0000 PEEE [1:0] PEEE – PWM output Enable and External input Enable 00 : PWM output is disable and external input is disable. 01 : PWM output is disable and external input is enable.

  • Page 259: Channel-6 Periodic Mode Register (Pwmch6Pdmr)

    Reset value : 0x0000_0000 [31:0] CR – Capture Register Capture register. The CR is loaded with the value of the TC when external input signal is triggered. Channel-6 Periodic Mode Register (PWMCH6PDMR) Base address : 0x4000_5600 Address offset : 0x34 Reset value : 0x0000_0000 [0] PDM –...

  • Page 260: Channel-6 Dead Zone Counter Register (Pwmch6Dzcr)

    [0] DZE – Dead Zone Enable 0 : Dead zone generation is disabled. 1 : Dead zone generation is enabled. Channel-6 Dead Zone Counter Register (PWMCH6DZCR) Base address : 0x4000_5600 Address offset : 0x3C Reset value : 0x0000_0000 [9:0] DZC – Dead Zone Counter value Dead zone generation counter value register.

  • Page 261: Register Map

    21.17 Register map The following Table 23 summarizes the PWM Channel-5 registers. Table 23 PWM channel 6 register map and reset values Offset Register 비고 PWMCH6IR Channel-6 interrupt register 0x00 reset value PWMCH6IER Channel-6 interrupt enable register 0x04 reset value PWMCH6ICR Channel-6 interrupt clear register 0x08...

  • Page 262: Pwm Channel-7 Registers (Base Address : 0X4000_5700)

    21.18 PWM Channel-7 Registers (Base address : 0x4000_5700) Channel-7 interrupt register(PWMCH7IR) Base address : 0x4000_5700 Address offset : 0x00 Reset value : 0x0000_0000 [0] MI – Match Interrupt This bit is set by hardware and cleared by interrupt clear register. O : Match interrupt does not occur.

  • Page 263: Channel-7 Interrupt Clear Register(Pwmch7Icr)

    [0] MIE – Match Interrupt Enabled. O : Match interrupt is not enabled. 1 : Match interrupt is enabled. [1] OIE – Overflow Interrupt Enable. O : Overflow interrupt is not enabled. 1 : Overflow interrupt is enabled. [2] CIE – Capture Interrupt Enable. O : Capture interrupt is not enabled.

  • Page 264: Channel-7 Prescale Counter Register (Pwmch7Pcr)

    [31:0] TCR – Timer/Counter register Timer/Counter register. These register hold the current values of the Timer/Counter(TC). The TC is incremented every PR cycles. When the TC is reached to value of match register, the match interrupt is occurred and PWM output waveform becomes 0.

  • Page 265: Channel-7 Match Register (Pwmch7Mr)

    [5:0] PR – Prescale Register Prescale register. The PC is incremented when the PC is reached to the PR. Channel-7 Match Register (PWMCH7MR) Base address : 0x4000_5700 Address offset : 0x18 Reset value : 0x0000_0000 [31:0] MR – Match Register Match register.

  • Page 266: Channel-7 Up-Down Mode Register (Pwmch7Udmr)

    Channel-7 Up-Down Mode Register (PWMCH7UDMR) Base address : 0x4000_5700 Address offset : 0x20 Reset value : 0x0000_0000 [0] UDM – Up-Down mode 0 : TC runs up count. 1 : TC runs down count. Channel-7 Timer/Counter Mode Register (PWMCH7TCMR) Base address : 0x4000_5700 Address offset : 0x24 Reset value : 0x0000_0000 [1:0] TCM –...

  • Page 267: Channel-7 Pwm Output Enable And External Input Enable Register (Pwmch7Peeer)

    Channel-7 PWM output Enable and External input Enable Register (PWMCH7PEEER) Base address : 0x4000_5700 Address offset : 0x28 Reset value : 0x0000_0000 PEEE [1:0] PEEE – PWM output Enable and External input Enable 00 : PWM output is disable and external input is disable. 01 : PWM output is disable and external input is enable.

  • Page 268: Channel-7 Periodic Mode Register (Pwmch7Pdmr)

    Reset value : 0x0000_0000 [31:0] CR – Capture Register Capture register. The CR is loaded with the value of the TC when external input signal is triggered. Channel-7 Periodic Mode Register (PWMCH7PDMR) Base address : 0x4000_5700 Address offset : 0x34 Reset value : 0x0000_0000 [0] PDM –...

  • Page 269: Channel-7 Dead Zone Counter Register (Pwmch7Dzcr)

    [0] DZE – Dead Zone Enable 0 : Dead zone generation is disabled. 1 : Dead zone generation is enabled. Channel-7 Dead Zone Counter Register (PWMCH7DZCR) Base address : 0x4000_5700 Address offset : 0x3C Reset value : 0x0000_0000 [9:0] DZC – Dead Zone Counter value Dead zone generation counter value register.

  • Page 270: Register Map

    21.19 Register map The following Table 24 summarizes the PWM Channel-5 registers. Table 24 PWM channel 7 register map and reset values Offset Register 비고 PWMCH7IR Channel-7 interrupt register 0x00 reset value PWMCH7IER Channel-7 interrupt enable register 0x04 reset value PWMCH7ICR Channel-7 interrupt clear register 0x08...

  • Page 271: Pwm Common Registers (Base Address : 0X4000_5800)

    21.20 PWM Common Registers (Base address : 0x4000_5800) Interrupt Enable Register (IER) Base address : 0x4000_5800 Address offset : 0x00 Reset value : 0x0000_0000 [0] IE0 – Channel 0 Interrupt Enable 0 : Channel 0 interrupt is disabled. 1 : Channel 0 interrupt is enabled. [1] IE1 –...

  • Page 272: Start/Stop Register (Ssr)

    Start/Stop Register (SSR) Base address : 0x4000_5800 Address offset : 0x04 Reset value : 0x0000_0000 [0] SS0 – Channel 0 Timer/Counter Start or Stop. 0 : Timer/Counter stop. 1 : Timer/Counter start. [1] SS1 – Channel 1 Timer/Counter Start or Stop. 0 : Timer/Counter stop.

  • Page 273: Pause Register (Psr)

    Pause Register (PSR) Base address : 0x4000_5800 Address offset : 0x04 Reset value : 0x0000_0000 The Timer/Counter is paused after TC is reached to value of limit register. [0] PS0 – Channel 0 Timer/Counter Pause. 0 : Timer/Counter is not paused. 1 : Timer/Counter is paused.

  • Page 274: Register Map

    21.21 Register map The following Table 25 summarizes the PWM Common registers. Table 25 PWM common register map and reset values Offset Register 비고 Interrupt enable register 0x00 reset value Start/Stop register 0x04 reset value Pause register 0x08 reset value 274 / 399 W7500x Reference Manual Version1.1.0...

  • Page 275: Dual Timers

    Dual timers 22.1 Introduction The dual timer consists two programmable 32-bit or 16-bit Free-running counters(FRCs) that can generate interrupts when they reach 0. There are two dual timers and 4 FRCs. One dual timers has one interrupt handler, resulting in two interrupts of timers. Also one dual timer has one clock but two clock enable signals.

  • Page 276: Functional Description

    22.3 Functional description Clock and clock enable The dual timers contain PCLK and TIMERCLK clock inputs. PCLK is the main APB system clock and is used by the register interface. TIMERCLK is the input to the prescale units and the decrementing counters.

  • Page 277: Interrupt

    Periodic mode The counter generates an interrupt at a constant interval, reloading the original value after wrapping past zero. Interrupt An interrupt is generated when the counter reaches 0 and is only cleared when the interrupt clear register is accessed. The register holds the value until the interrupt is cleared.

  • Page 278: How To Set The Dual Timers

    How to set the dual timers Set the clock enable Set the Load register Timer size : 16-bit or 32-bit 16-bit : TimerControl[1] = 0 32-bit : TimerControl[1] = 1 Prescale : 1, 16, or 256 1 : TimerControl[3:2] = 0 16 : TimerControl[3:2] = 1 256 : TimerControl[3:2] = 2 Interrupt :...

  • Page 279: Dual Timer0_0 Registers (Base Address : 0X4000_1000)

    22.4 Dual timer0_0 Registers (Base address : 0x4000_1000) Timer0_0 Load Register(DUALTIMER0_0TimerLoad) Base address : 0x4000_1000 Address offset : 0x00 Reset value : 0x0000_0000 [31:0] TLR – Timer Load Register This register contains the value from which the counter is to decrement. This is the value used to reload the counter when Periodic mode is enabled, and the current count reaches 0.

  • Page 280: Timer0_0 Interrupt Clear Register (Dualtimer0_0Timerintclr)

    [0] OC – One-shot Count 0 : Wrapping mode, default. 1 : One-shot mode. [1] TS – Timer Size 0 : 16-bit counter, default. 1 : 32-bit counter. [3:2] TP – Timer Prescale. 00 : 0 stages of prescale, clock is divided by 1, default. 01 : 4 stages of prescale, clock is divided by 16.

  • Page 281: Timer0_0 Masked Interrupt Status Register (Dualtimer0_0Timermis)

    Reset value : 0x0000_0000 [0] RIS – Raw Interrupt Status Register This register indicates the raw interrupt status from the counter. This value is ANDed with the timer interrupt enable bit from the Timer Control Register to create the masked interrupt, that is passed to the interrupt output pin. Timer0_0 Masked Interrupt Status Register (DUALTIMER0_0TimerMIS) Base address : 0x4000_1000...
  • Page 282 [31:0] BGL – Background Load Register This register contains the value from which the counter is to decrement. This is the value used to reload the counter when Periodic mode is enabled, and the current count reaches 0. This register provides an alternative method of accessing the TimerLoad Register.

  • Page 283: Register Map

    22.5 Register map The following Table 26 summarizes the Dual timer 0_0 registers. Table 26 Dual timer 0_0 register map and reset values Offset Register 비고 DUALTIMER0_0TimerLoad Timer0_0 Load Register 0x00 reset value DUALTIMER0_0TimerValue Timer0_0 Value Register 0x04 reset value DUALTIMER0_0TimerControl Timer0_0 Control Register 0x08...

  • Page 284: Dual Timer0_1 Registers (Base Address : 0X4000_1020)

    22.6 Dual timer0_1 Registers (Base address : 0x4000_1020) Timer0_1 Load Register(DUALTIMER0_1TimerLoad) Base address : 0x4000_1020 Address offset : 0x00 Reset value : 0x0000_0000 [31:0] TLR – Timer Load Register This register contains the value from which the counter is to decrement. This is the value used to reload the counter when Periodic mode is enabled, and the current count reaches 0.

  • Page 285: Timer0_1 Interrupt Clear Register (Dualtimer0_1Timerintclr)

    [0] OC – One-shot Count 0 : Wrapping mode, default. 1 : One-shot mode. [1] TS – Timer Size 0 : 16-bit counter, default. 1 : 32-bit counter. [3:2] TP – Timer Prescale. 00 : 0 stages of prescale, clock is divided by 1, default. 01 : 4 stages of prescale, clock is divided by 16.

  • Page 286: Timer0_1 Masked Interrupt Status Register (Dualtimer0_1Timermis)

    [0] RIS – Raw Interrupt Status Register This register indicates the raw interrupt status from the counter. This value is ANDed with the timer interrupt enable bit from the Timer Control Register to create the masked interrupt, that is passed to the interrupt output pin. Timer0_1 Masked Interrupt Status Register (DUALTIMER0_1TimerMIS) Base address : 0x4000_1020...
  • Page 287 [31:0] BGL – Background Load Register This register contains the value from which the counter is to decrement. This is the value used to reload the counter when Periodic mode is enabled, and the current count reaches 0. This register provides an alternative method of accessing the TimerLoad Register.

  • Page 288: Register Map

    22.7 Register map The following Table 27 summarizes the Dual timer 0_1 registers. Table 27 Dual timer 0_1 register map and reset values Offset Register 비고 DUALTIMER0_1TimerLoad Timer0_1 Load Register 0x00 reset value DUALTIMER0_1TimerValue Timer0_1 Value Register 0x04 reset value DUALTIMER0_1TimerControl Timer0_1 Control Register 0x08...

  • Page 289: Dual Timer 0 Clock Enable Register (Base Address : 0X4000_1080)

    22.8 Dual Timer 0 Clock Enable Register (Base address : 0x4000_1080) Timer0_0 Clock Enable Register (TIMCLKEN0_0) Base address : 0x4000_1080 Address offset : 0x00 Reset value : 0x0000_0000 [0] CE – Clock Enable Register 0 : Clock disable 1 : Clock enable Timer0_1 Clock Enable Register (TIMCLKEN0_1) Base address : 0x4000_1080 Address offset : 0x20...

  • Page 290: Register Map

    22.9 Register map The following Table 28 summarizes the Dual timer 0 registers. Table 28 Dual timer 0 clock enable register map and reset values 290 / 399 W7500x Reference Manual Version1.1.0...

  • Page 291: Dual Timer1_0 Registers (Base Address : 0X4000_2000)

    22.10 Dual timer1_0 Registers (Base address : 0x4000_2000) Timer1_0 Load Register(DUALTIMER1_0TimerLoad) Base address : 0x4000_2000 Address offset : 0x00 Reset value : 0x0000_0000 [31:0] TLR – Timer Load Register This register contains the value from which the counter is to decrement. This is the value used to reload the counter when Periodic mode is enabled, and the current count reaches 0.

  • Page 292: Timer1_0 Interrupt Clear Register (Dualtimer1_0Timerintclr)

    0 : Wrapping mode, default. 1 : One-shot mode. [1] TS – Timer Size 0 : 16-bit counter, default. 1 : 32-bit counter. [3:2] TP – Timer Prescale. 00 : 0 stages of prescale, clock is divided by 1, default. 01 : 4 stages of prescale, clock is divided by 16.

  • Page 293: Timer1_0 Masked Interrupt Status Register (Dualtimer1_0Timermis)

    [0] RIS – Raw Interrupt Status Register This register indicates the raw interrupt status from the counter. This value is ANDed with the timer interrupt enable bit from the Timer Control Register to create the masked interrupt, that is passed to the interrupt output pin. Timer1_0 Masked Interrupt Status Register (DUALTIMER1_0TimerMIS) Base address : 0x4000_2000...
  • Page 294 This register contains the value from which the counter is to decrement. This is the value used to reload the counter when Periodic mode is enabled, and the current count reaches 0. This register provides an alternative method of accessing the TimerLoad Register.

  • Page 295: Register Map

    22.11 Register map The following Table 29 summarizes the Dual timer 1_0 registers. Table 29 Dual timer 1_0 register map and reset values Offset Register 비고 DUALTIMER1_0TimerLoad Timer1_0 Load Register 0x00 reset value DUALTIMER1_0TimerValue Timer1_0 Value Register 0x04 reset value DUALTIMER1_0TimerControl Timer1_0 Control Register 0x08...

  • Page 296: Dual Timer1_1 Registers (Base Address : 0X4000_2020)

    22.12 Dual timer1_1 Registers (Base address : 0x4000_2020) Timer1_1 Load Register(DUALTIMER1_1TimerLoad) Base address : 0x4000_2020 Address offset : 0x00 Reset value : 0x0000_0000 [31:0] TLR – Timer Load Register This register contains the value from which the counter is to decrement. This is the value used to reload the counter when Periodic mode is enabled, and the current count reaches 0.

  • Page 297: Timer1_1 Interrupt Clear Register (Dualtimer1_1Timerintclr)

    0 : Wrapping mode, default. 1 : One-shot mode. [1] TS – Timer Size 0 : 16-bit counter, default. 1 : 32-bit counter. [3:2] TP – Timer Prescale. 00 : 0 stages of prescale, clock is divided by 1, default. 01 : 4 stages of prescale, clock is divided by 16.

  • Page 298: Timer1_1 Masked Interrupt Status Register (Dualtimer1_1Timermis)

    [0] RIS – Raw Interrupt Status Register This register indicates the raw interrupt status from the counter. This value is ANDed with the timer interrupt enable bit from the Timer Control Register to create the masked interrupt, that is passed to the interrupt output pin. Timer1_1 Masked Interrupt Status Register (DUALTIMER1_1TimerMIS) Base address : 0x4000_2020...
  • Page 299 [31:0] BGL – Background Load Register This register contains the value from which the counter is to decrement. This is the value used to reload the counter when Periodic mode is enabled, and the current count reaches 0. This register provides an alternative method of accessing the TimerLoad Register.

  • Page 300: Register Map

    22.13 Register map The following Table 30 summarizes the Dual timer 1_1 registers. Table 30 Dual timer 1_1 register map and reset values Offset Register 비고 DUALTIMER1_1TimerLoad Timer1_1 Load Register 0x00 reset value DUALTIMER1_1TimerValue Timer1_1 Value Register 0x04 reset value DUALTIMER1_1TimerControl Timer1_1 Control Register 0x08...

  • Page 301: Dual Timer 1 Clock Enable Register (Base Address : 0X4000_2080)

    22.14 Dual Timer 1 Clock Enable Register (Base address : 0x4000_2080) Timer1_0 Clock Enable Register (TIMCLKEN1_0) Base address : 0x4000_2080 Address offset : 0x00 Reset value : 0x0000_0000 [0] CE – Clock Enable Register 0 : Clock disable 1 : Clock enable Timer1_1 Clock Enable Register (TIMCLKEN1_1) Base address : 0x4000_2080 Address offset : 0x20...

  • Page 302: Register Map

    22.15 Register map The following Table 31 summarizes the Dual timer 1 registers. Table 31 Dual timer 1 clock enable register map and reset values Watchdog timer 23.1 Introduction The watchdog is based on a 32-bit down-counter that is initialized from the Reload Register, WDTLoad.

  • Page 303: Interrupt And Reset Request

    PCLK is the main APB system clock and is used by the register interface. Interrupt and reset request An interrupt is generated when the counter reaches 0 and is only cleared when the interrupt clear register is accessed. The register holds the value until the interrupt is cleared. Reset request is asserted when the counter reaches 0 repeatedly and is not reprogrammed.

  • Page 304: Watchdog Timer Value Register(Wdtvalue)

    Watchdog timer Value Register(WDTValue) Address offset : 0x004 Reset value : 0xFFFF_FFFF [31:0] WVR – Watchdog timer Value Register. This register gives the current value of the decrementing counter. Watchdog timer Control Register(WDTControl) Address offset : 0x008 Reset value : 0x0000_0000 [0] IEN –...

  • Page 305: Watchdog Timer Raw Interrupt Status Register (Wdtris)

    [0] WIC – Watchdog timer Interrupt Clear A write of 1 to this register clears the watchdog interrupt, and reloads the counter from the value in WDTLoad. Watchdog timer Raw Interrupt Status Register (WDTRIS) Address offset : 0x010 Reset value : 0x0000_0000 [0] RIS –...

  • Page 306: Watchdog Timer Lock Register(Wdtlock)

    Watchdog timer Lock Register(WDTLock) Address offset : 0xC00 Reset value : 0x0000_0000 This register disables write accesses to all other registers. This is to prevent rogue software from disabling the watchdog functionality. Writing a value of 0x1ACCE551 enables write access to all other registers. Writing any other value disables write accesses.

  • Page 307: Register Map

    23.5 Register map The following Table 32 summarizes the Watchdog timer registers. Table 32 Watchdog Timer register map and reset values Offset Register 비고 Watchdog timer Load WDTLoad 0x000 Register reset value Watchdog timer Value WDTValue Register 0x004 reset value Watchdog timer Control WDTControl Register...

  • Page 308: Rtc Clock

    RTCCLK 1Hz Clock Divider RTC BCD Counter DIVRST Counter Increment Counter Counter Interrupt Consolidated Interrupt Pending interrupt clear Alarm Match Interrupt Alarm INTEN Interrupt Pending clear PreBCD Figure 42. RTC block diagram RTC clock RTC Clock (RTCCLK) can be selected among several clocks (32768Hz oscillator, MCLK, RCLK, OCLK).

  • Page 309: Rtc Setting Flow

    RTC Setting flow RTC setting sequences are shown in flow chart. Figure 47 shows RTC setting flow for Counter Function. Figure 48 shows RTC setting flow for Alarm function. Figure 43. RTC setting flow for Counter Function 309 / 399 W7500x Reference Manual Version1.1.0...

  • Page 310: Rtc Registers (Base Address : 0X4000_E000)

    Initialize RTC module Enable RTC Wait for RTC clock stabilization time Select 32768Hz oscillator clock for RTC Set Current Time for RTC Set Alarm Time Enable RTC Alarm Interrupt Enable RTC Interrupt and Start Enable NVIC Power down (WFE) Wakeup by Alarm Interrupt Figure 44.

  • Page 311: Rtc Interrupt Mask Register (Rtcinte)

    INTEN DIVRST CLKEN [0] CLKEN – Clock Enable This bit written by S/W to enable or disable clock 0 : The time counters are disabled (clock stop) 1 : The time counters are enabled (clock enable) [1] DIVRST – RTC Divider Reset This bit set and cleared by S/W to reset RTC divider.
  • Page 312 This bit set and cleared by S/W to enable or disable RTC Minute interrupt. 0 : No effect 1 : an increment of the Minute value generates an interrupt [2] IMHOUR – RTC Hour Interrupt Enable This bit set and cleared by S/W to enable or disable RTC Hour interrupt. 0 : No effect 1 : an increment of the Hour value generates an interrupt [3] IMDATE –...

  • Page 313: Rtc Interrupt Pending Register (Rtcintp)

    [6] AINT – RTC Alarm Interrupt Enable This bit set and cleared by S/W to enable or disable RTC Alarm interrupt. 0 : No effect 1 : Alarm interrupt enabled RTC Interrupt Pending register (RTCINTP) Address offset: 0x0008 Reset value: 0x0000_0000 Bit [0] RTCCIF –...

  • Page 314: Rtc Alarm Mask Register (Rtcamr)

    RTC Alarm Mask register (RTCAMR) Address offset: 0x000C Reset value: 0x0000_0000 [0] AMRSEC – RTC Alarm Mask for Second This bit set and cleared by S/W to enable or disable comparison for Second 0 : No effect 1 : the Second value is compared to the Predetermining Second for the alarm [1] AMRMIN –...

  • Page 315: Rtc Bcd Second Register (Bcdsec)

    0 : No effect 1 : the Date value is compared to the Predetermining Date for the alarm RTC BCD Second register (BCDSEC) Address offset: 0x0010 Reset value: 0x0000_0000 BCDSEC Bit [6:0] BCDSEC – RTC Seconds value (0 to 59) RTC BCD Minute register (BCDMIN) Address offset: 0x0014 Reset value: 0x0000_0000...

  • Page 316: Rtc Bcd Day Register (Bcdday)

    Bit [5:0] BCDHOUR – RTC Hour value (0 to 23) RTC BCD Day register (BCDDAY) Address offset: 0x001C Reset value: 0x0000_0000 BCDDAY Bit [3:0] BCDDAY – RTC Day of Week value (1 to 7) RTC BCD Date register (BCDDATE) Address offset: 0x0020 Reset value: 0x0000_0000 BCDDATE Bit [5:0] BCDDATE –...

  • Page 317: Rtc Bcd Year Register (Bcdyear)

    Bit [4:0] BCDMON – RTC Month value (1 to 12) RTC BCD Year register (BCDYEAR) Address offset: 0x0028 Reset value: 0x0000_0000 BCDYEAR Bit [15:0] BCDYEAR – RTC Year value (0 to 4095) RTC Predetermining Second register (PRESEC) Address offset: 0x002C Reset value : 0xXXXX_XXXX, NC PRESEC Bit [6:0] PRESEC –...

  • Page 318: Rtc Predetermining Hour Register (Prehour)

    RTC Predetermining Hour register (PREHOUR) Address offset: 0x0034 Reset value : 0xXXXX_XXXX, NC PREHOUR Bit [5:0] PREHOUR – RTC Predetermining Hour value (0 to 23) RTC Predetermining Day register (PREDAY) Address offset: 0x0038 Reset value : 0xXXXX_XXXX, NC PREDAY Bit [3:0] PREDAY – RTC Predetermining Day of Week value (1 to 7) RTC Predetermining Date register (PREDATE) Address offset: 0x003C Reset value : 0xXXXX_XXXX, NC...

  • Page 319: Rtc Predetermining Month Register (Premon)

    RTC Predetermining Month register (PREMON) Address offset: 0x0040 Reset value : 0xXXXX_XXXX, NC PREMON Bit [4:0] PREMON – RTC Predetermining Month value (1 to 12) RTC Predetermining Year register (PREYEAR) Address offset: 0x0044 Reset value : 0xXXXX_XXXX, NC PREYEAR Bit [15:0] PREYEAR – RTC Predetermining Year value (0 to 4095) RTC Consolidated Time0 register (RTCTIME0) Address offset: 0x0048 Reset value : 0x0000_0000...

  • Page 320: Rtc Consolidated Time1 Register (Rtctime1)

    Bit [21:16] CBCDHOUR – RTC Consolidated Hour value (0 to 23) Bit [27:24] CBCDDAY – RTC Consolidated Day of Week value (1 to 7) RTC Consolidated Time1 register (RTCTIME1) Address offset: 0x004C Reset value : 0x0000_0000 CBCDYEAR CBCDMON CBCDDATE Bit [5:0] CBCDDATE – RTC Consolidated Day of Month value (1 to 28, 29, 30, or 31) Bit [12:8] CBCDMON –...

  • Page 321: Register Map

    24.5 Register map Table 33 RTC register map and reset values Offset Register Note RTCCON Control register 0x00 reset value RTCINTE Interrupt Mask register 0x04 reset value RTCINTP Interrupt Pending register 0x08 reset value RTCAMR Alarm Mask register 0x0C reset value BCDSEC BCDSEC BCD Second register...

  • Page 322: Uart(Universal Asynchronous Receive Transmit)

    Offset Register Note PRESEC PRESEC Predetermining Second register 0x2C reset value nc nc nc nc nc nc nc PREMIN PREMIN Predetermining Minute register 0x30 reset value nc nc nc nc nc nc nc PREHOUR PREHOUR Predetermining Hour register 0x34 reset value nc nc nc nc nc nc PREDAY Predetermining Day register...

  • Page 323: Functional Description

    25.3 Functional description UART bidirectional communication requires a minimum of two pins: RX, TX The frame are comprised of:  An Idle Line prior to transmission or reception  A start bit  A data word (8 or 9 bits) least significant bit first ...
  • Page 324 Figure 46. UART character frame 324 / 399 W7500x Reference Manual Version1.1.0...

  • Page 325: Baud Rate Calculation

    Baud rate calculation UARTx can operate with or without using the Fractional Divider. The baud rate divisor is a 22- bit number consisting the UARTxIBRD(16-bit integer) and the UARTxFBRD(6-bit fractional). This is used by the baud rate generator to determine the bit period. UARTCLK Baud Rate Divisor = = ������...

  • Page 326: Data Transmission

    Data transmission Data transmitted is stored in a 32-byte FIFOs. Transmit data is written into the transmit FIFO for transmission. If UART is enabled, it causes a data frame to start transmitting with parameters indicated in the UARTxLCR_H. Data continues to transmit until there is no data left in the transmit FIFO. The BUSY bit of UARTxFR is ‘1’...

  • Page 327: Hardware Flow Control

    Hardware flow control Figure 50. Hardware flow control description The RTS flow control is enabled by setting the RTSen of UARTxCR. If RTS is enabled, the data flow is controlled as follows. When the receiver FIFO level reaches the programmed trigger level, nUARTRTS(pin) is asserted(to a low value).

  • Page 328: Uart0 Registers(Base Address: 0X4000_C000)

    Figure 52 shows how software should use the RTS/CTR. Initia l setting Set RTS/CTS of UARTxCR Set FEN of UARTxLCR_H Set RxSel/TxSel of UARTxIFLS CTS of UARTxFR =0? RXFE of UARTxFR =0? Send Tx da ta receive Rx da ta BUSY of UARTxFR =1? Figure 52.

  • Page 329: Uart0Rsr/Ecr (Uart0 Receive Status Register/Error Clear Register)

    The write operation initiates transmission from the UART. The data is prefixed with a start bit, appended with the appropriate parity bit(if parity is enabled), and a stop bit. The resultant word is then transmitted. The received data byte is read by performing reads from the UARTDR register along with the corresponding status information.

  • Page 330: Uart0Fr (Uart0 Flag Register)

    [3] OE – Overrun error This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UART0ECR [2] BE – Break error This bit is cleared to 0 by a write to UART0ECR [1] PE –...

  • Page 331: Uart0Ilpr (Uart0 Irda Low-Power Counter Register)

    [6] RXFF – Receive FIFO full This bit depends on the state of the FEN bit in the line control register, UARTLCR_H. 0: The bit is set when the receive holding register is full 1: The bit is set when the receive FIFO is full [5] TXFF –...

  • Page 332: Uart0Ibrd (Uart0 Integer Baud Rate Register)

    These bits are cleared to 0 at reset. ILPDVSR = (�� /�� �������������� ����������������16 Where, �� is nominally 1.8432MHz ����������������16 The divisor is 1.42MHz < �� < 2.12MHz, results in a low-power pulse duration of 1.41 ����������������16 – 2.11us. UART0IBRD (UART0 Integer Baud Rate Register) Address offset: 0x0024 Reset value: 0x00 The UART0IBRD Register is the integer part of the baud rate divisor value.

  • Page 333: Uart0Lcr_H (Uart0 Line Control Register)

    The BAUDDIV is comprised of the integer value (BAUD DIVINT) and the fractional value (BAUD DIVFRAC). Example 1 If the required baud rate is 115200 and UARTCLK = 8MHz then: Baud rate divisor = (8 × 10 )/(16 × 115200) = 4.340278 This means BRD = 4 and BRD = 0.340278...

  • Page 334: Uart0Cr (Uart0 Control Register)

    The parity bit is transmitted and checked as a 1 when EPS bit set ‘0’ The parity bit is transmitted and checked as a 0 when EPS bit set ‘1’ [6:5] WLEN – Word length 5 bits 6 bits 7 bits 8 bits [4] FEN –...
  • Page 335 [15] CTSEn – CTS hardware flow control enable. 1: CTS hardware flow control is enable. Data is only transmitted when the UART0CTS signal is asserted. [14] RTSEn – RTS hardware flow control enable 1: RTS hardware flow control is enable. Data is only requested when there is space in the receive FIFO for it to be received.

  • Page 336: Uart0Ifls (Uart0 Interrupt Fifo Level Select Register)

    [0] UARTEN –UART enable 0: UART is disabled 1: UART is enabled Program the control registers as follows: 1. Disable the UART. 2. Wait for the end of transmission or reception of the current character. 3. Flush the transmit FIFO by setting the FEN bit to 0 in the Line Control Register, UARTLCR_H.
  • Page 337 In other words, if a bit of UART0IMSC is ‘0’, an interrupt will not be issued even if the corresponding bit of interrupt register is ‘1’. RIMI OEIM BEIM PEIM FEIM RTIM TXIM RXIM [10] OEIM – Overrun error interrupt mask 0: Disable UART0OEINTR 1: Enable UART0OEINTR [9] BEIM –...

  • Page 338: Uart0Ris (Uart0 Raw Interrupt Status Register)

    0: Disable UART0CRSINTR 1: Enable UART0CRSINTR [0] RIMIM – nUART0RI modem interrupt mask 0: Disable UART0RIINTR 1: Enable UART0RIINTR UART0RIS (UART0 Raw Interrupt Status Register) Address offset: 0x003C Reset value: 0x00- The UART0RIS register indicates the raw interrupt status register. CTSR RMIS RMIS...

  • Page 339: Uart0Mis (Uart0 Masked Interrupt Status Register)

    [0] RIRMIS – nUART0RI modem interrupt status It indicates state of the UART0RIINTR interrupt. UART0MIS (UART0 Masked Interrupt Status Register) Address offset: 0x0040 Reset value: 0x00- The UART0MIS register is the masked interrupt status register. MMIS MMIS MMIS MMIS [10] OEMIS – Overrun error masked interrupt status It indicates state of the UART0OEINTR interrupt.

  • Page 340: Uart0Icr (Uart0 Interrupt Clear Register)

    UART0ICR (UART0 Interrupt Clear Register) Address offset: 0x0044 Reset value: - The UART0ICR register is the interrupt clear register and is write-only. OEIC BEIC PEIC FEIC RTIC TXIC RXIC [10] OEIC – Overrun error interrupt clear Clear the UART0OEINTR interrupt. [9] BEIC –...

  • Page 341: Register Map

    25.5 Register map The following Table 34 summarizes the UART0 registers. Table 34 UART0 register map and reset values Offset Register 비고 DATA UART0DR Data Register 0x000 reset value UART0RSR/ Receive Status/Error Clear Register UART0ECR 0x004 reset value UART0FR Flage Register 0x018 reset value 0x020...

  • Page 342: Uart1 Registers(Base Address: 0X4000_D000)

    25.6 UART1 Registers(Base address: 0x4000_D000) UART1DR (UART1 Data Register) Address offset: 0x000 Reset value: 0x0000_0000 The UART1DR is the data register. The write operation initiates transmission from the UART. The data is prefixed with a start bit, appended with the appropriate parity bit(if parity is enabled), and a stop bit. The resultant word is then transmitted.

  • Page 343: Uart1Fr (Uart1 Flag Register)

    Receive status can also be read from the UART1RSR register. A write to the UART1ECR register clears the framing, parity, break, and overrun errors. [3] OE – Overrun error This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UART1ECR [2] BE –...

  • Page 344: Uart1Ilpr (Uart1 Irda Low-Power Counter Register)

    [7] TXFE – Transmit FIFO empty This bit depends on the state of the FEN bit in the line control register, UARTLCR_H. 0: The bit is set when transmit holding register is empty. 1: The bit is set when transmit FIFO is empty [6] RXFF –...

  • Page 345: Uart1Ibrd (Uart1 Integer Baud Rate Register)

    [7:0] ILPDVSR – 8-bit low-power divisor value These bits are cleared to 0 at reset ILPDVSR = (�� /�� �������������� ����������������16 Where, �� is nominally 1.8432MHz ����������������16 The divisor is 1.42MHz < �� < 2.12MHz, results in a low-power pulse duration of 1.41 ����������������16 –...

  • Page 346: Uart1Lcr_H (Uart1 Line Control Register)

    The baud rate divisor is calculated as follows: Baud rate divisor BAUDDIV = (�� /(16 × �������� ��������)) �������������� Where, �� is the UART reference clock frequency. �������������� The BAUDDIV is comprised of the integer value (BAUD DIVINT) and the fractional value (BAUD DIVFRAC).

  • Page 347: Uart1Cr (Uart1 Control Register)

    [7] SPS – Stick parity select 0: stick parity is disable 1: either: The parity bit is transmitted and checked as a 1 when EPS bit set ‘0’ The parity bit is transmitted and checked as a 0 when EPS bit set ‘1’ [6:5] WLEN –...
  • Page 348 CTSEn RTSEn Out2 Out1 SIRLP SIREN UARTEN [15] CTSEn – CTS hardware flow control enable. 1: CTS hardware flow control is enable. Data is only transmitted when the UART1CTS signal is asserted. [14] RTSEn – RTS hardware flow control enable 1: RTS hardware flow control is enable.

  • Page 349: Uart1Ifls (Uart1 Interrupt Fifo Level Select Register)

    0: IrDA SIR ENDEC is disable 1: IrDA SIR ENDEC is enable [0] UARTEN – UART enable 0: UART is disabled 1: UART is enabled Program the control registers as follows: 1. Disable the UART. 2. Wait for the end of transmission or reception of the current character. 3.
  • Page 350 The UART1IMSC register is the interrupt mask set/clear interrupts. When a bit of UART1IMSC is ‘1’ and the corresponding bit of interrupt register is ‘1’, an interrupt will be issued. In other words, if a bit of UART1IMSC is ‘0’, an interrupt will not be issued even if the corresponding bit of interrupt register is ‘1’.

  • Page 351: Uart1Ris (Uart1 Raw Interrupt Status Register)

    1: Enable UART1DCDINTR [1] CTSMIM – nUART1CTS modem interrupt mask 0: Disable UART1CRSINTR 1: Enable UART1CRSINTR [0] RIMIM – nUART1RI modem interrupt mask 0: Disable UART1RIINTR 1: Enable UART1RIINTR UART1RIS (UART1 Raw Interrupt Status Register) Address offset: 0x003C Reset value: 0x00- The UART1RIS register indicates the raw interrupt status register.

  • Page 352: Uart1Mis (Uart1 Masked Interrupt Status Register)

    [1] CTSRMIS – nUART1CTS modem interrupt status It indicates state of the UART1CTSINTR interrupt. [0] RIRMIS – nUART1RI modem interrupt status It indicates state of the UART1RIINTR interrupt. UART1MIS (UART1 Masked Interrupt Status Register) Address offset: 0x0040 Reset value: 0x00- The UART1MIS register is the masked interrupt status register.

  • Page 353: Uart1Icr (Uart1 Interrupt Clear Register)

    It indicates state of the UART1RIINTR interrupt. UART1ICR (UART1 Interrupt Clear Register) Address offset: 0x0044 Reset value: - The UART1ICR register is the interrupt clear register and is write-only. DSRM DCDM CTSM OEIC BEIC PEIC FEIC RTIC TXIC RXIC [10] OEIC – Overrun error interrupt clear Clear the UART1OEINTR interrupt.

  • Page 354: Register Map

    25.7 Register map The following Table 35 summarizes the UART1 registers. Table 35 UART1 register map and reset values Offset Register 비고 DATA UART1DR Data Register 0x000 reset value UART1RSR/ Receive Status/Error Clear Register UART1ECR 0x004 reset value UART1FR Flage Register 0x018 reset value 0x020...

  • Page 355: Universal Asynchronous Receive Transmit(Uart2)

    Universal Asynchronous Receive Transmit(UART2) 26.1 Introduction The UART2 supports Asynchronous one-way communication, half-duplex single wire communication, and without CTS/RTS. UART2 is called the simple UART. 26.2 Feature Serial-to-parallel conversion on data received from a peripheral device Parallel-to-serial conversion on data transmitted to the peripheral device 26.3 Functional description UART bidirectional communication requires a minimum of two pins: RX, TX The frame are comprised of:...
  • Page 356 Figure 54 show how to set the UART Initial value. Figure 54. UART2 Initial setting flow chart 356 / 399 W7500x Reference Manual Version1.1.0...

  • Page 357: Uart2 Registers(Base Address: 0X4000_6000)

    26.4 UART2 Registers(Base address: 0x4000_6000) UART2DR (UART2 Data Register) Address offset: 0x000 Reset value: 0x0000_0000 The UART2DR is the data register. The write operation initiates transmission from the UART2. The received data byte is read by performing reads from the UART2DR register along with the corresponding status information. DATA [7:0] DATA –...

  • Page 358: Uart2Cr (Uart2 Control Register)

    Read Only 0: The bit is set when transmit holding register is full. 1: The bit is set when transmit buffer is full. UART2CR (UART2 Control Register) Address offset: 0x008 Reset value: 0x0000_0000 The UART2CR is the control register. ROIE TOIE RXIE TXIE...

  • Page 359: Uart2Bdr (Uart2 Baud Rate Divider Register)

    RXOI TXOI [3] RXOI –Receive Overrun Interrupt This bit depends on the state of the ROIE bit in the control register, UART2CR [2] TXOI – Transmit Overrun Interrupt This bit depends on the state of the TOIE bit in the control register, UART2CR [1] RXI –...

  • Page 360: Register Map

    26.5 Register map The following Table 36 summarizes the UART2 registers. Table 36 UART2 register map and reset values 360 / 399 W7500x Reference Manual Version1.1.0...

  • Page 361: Synchronous Serial Port (Ssp)

    Synchronous Serial Port (SSP) 27.1 Introduction The SSP block is an IP provided by ARM (PL022 “PrimeCell® Synchronous Serial Port”). Additional details about its functional blocks may be found in “ARM PrimeCell® Synchronous Serial Port (PL022) Technical Reference Manual”. 27.2 Features •...

  • Page 362: Functional Description

    27.3 Functional description Figure 55 shows the SSP block diagram. SSPTXINTR TxFIFO FIFO Status SSPINTR Interface Interrupt Generation RxFIFO SSPRXINTR SSPCLK SSPTXD SSPCLKOUT Transmit SSPCLKDIV Clock Register Prescale SSPCLKIN Prescaler value block Receive SSPRXD logic signals interface Figure 55. SSP block diagram Clock prescaler When configured as a master, an internal prescaler is used to provide the serial output clock.

  • Page 363: Receive Fifo

    Receive FIFO The common receive FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. Received data from the serial interface are stored in the buffer until it is read out by the CPU across the AMBA APB interface. When configured as a master or slave, serial data received through the SSPRXD pin is registered prior to parallel loading into the attached slave or master receive FIFO.

  • Page 364: Table 37 Dma Trigger Points For The Transmit And Receive Fifos

    Burst DMA transfer request, asserted by the SSP. This signal is asserted when  the receive FIFO contains four or more characters. SSPRXDMACLR DMA request clear asserted by the DMA controller to clear the receive request  signals. If DMA burst transfer is requested, the clear signal is asserted during the transfer of the last data in the burst.

  • Page 365: Interface Reset

    Watermark Transmit, number of empty locations Receive, number of filled locations level Figure 56 shows the timing diagram for both a single transfer request, and a burst transfer request, with the appropriate DMA clear signal. The signals are all synchronous to PCLK. PCLK DMASREQ DMABREQ...

  • Page 366: Enable Primecell Ssp Operation

    Enable PrimeCell SSP operation You can either prime the transmit FIFO, by writing up to eight 16-bit values when the PrimeCell SSP is disabled, or permit the transmit FIFO service request to interrupt the CPU. Once enabled, transmission or reception of data begins on the transmit, SSPTXD, and receive, SSPRXD, pins. Clock ratios There is a constraint on the ratio of the frequencies of PCLK to SSPCLK.

  • Page 367: Programming The Sspcr0 Control Register

    (min) => 12 x F (max), for slave mode. SSPCLK SSPCLKIN The maximum frequency of SSPCLK is calculated by the following equations, both of which must be satisfied: (max) <= 254 x 256 x F (min), for master mode SSPCLK SSPCLKOUT (max) <= 254 x 256 x F (min), for slave mode.

  • Page 368: Frame Format

    Set the Synchronous Serial Port Enable (SSE) bit to 1 to enable the operation of the PrimeCell SSP. Bit rate generation The serial bit rate is derived by dividing down the input clock SSPCLK. The clock is first divided by an even prescale value CPSDVSR in the range of 2-254, and is programmed in SSPCPSR. The clock is divided again by a value in the range of 1-256, that is 1 + SCR, where SCR is the value programmed in SSPCR0.

  • Page 369: Texas Instruments Synchronous Serial Frame Format

    For Texas Instruments synchronous serial frame format, the SSPFSSOUT pin is pulsed for one serial clock period starting at its rising edge prior to the transmission of each frame. For this frame format, both the PrimeCell SSP and the off-chip slave device drive their output data on the rising edge of SSPCLKOUT and latch data from the other device on the falling edge.

  • Page 370: Motorola Spi Frame Format

    Figure 58 shows the Texas Instruments synchronous serial frame format when back-to-back frames are transmitted. SSPCLKOUT/ SSPCLKIN SSPFSSOUT/ SSPFSSIN SSPTXD/ SSPRXD 4 to 16 bits nSSPOE (=0) Figure 58. Texas Instruments synchronous serial frame format, continuous transfers Motorola SPI frame format The Motorola SPI interface is a four-wire interface where the SSPFSSOUT signal behaves as a slave select.
  • Page 371 SSPCLKOUT/ SSPCLKIN SSPFSSOUT/ SSPFSSIN SSPRXD 4 to 16 bits nSSPOE SSPTXD Figure 59 Motorola SPI frame format, single transfer, with SPO=0 and SPH=0 Figure 60 shows a continuous transmission signal sequence for Motorola SPI frame format with SPO=0, SPH=0. SSPCLKOUT/ SSPCLKIN SSPFSSOUT/ SSPFSSIN...
  • Page 372 One half SSPCLKOUT period later, valid master data is transferred to the SSPTXD pin. Now that both the master and slave data have been set, the SSPCLKOUT master clock pin goes HIGH after one additional half SSPCLKOUT period. The data is now captured on the rising and propagated on the falling edges of the SSPCLKOUT signal.
  • Page 373 • the nSSPOE pad enable signal is forced HIGH, making the transmit pad high impedance • when the PrimeCell SSP is configured as a master, the nSSPCTLOE line is driven LOW, enabling the SSPCLKOUT pad, active-LOW enable • when the PrimeCell SSP is configured as a slave, the nSSPCTLOE line is driven HIGH, disabling the SSPCLKOUT pad, active-LOW enable.
  • Page 374 SSPCLKOUT/ SSPCLKIN SSPFSSOUT/ SSPFSSIN SSPTXD/ SSPRXD 4 to 16 bits nSSPOE (=0) Figure 63. Motorola SPI frame format, continuous transfers, with SPO=1 and SPH=0 In this configuration, during idle periods: • the SSPCLKOUT signal is forced HIGH • the SSPFSSOUT signal is forced HIGH •...
  • Page 375 transfer, the SSPFSSOUT pin is returned to its idle state one SSPCLKOUT period after the last bit has been captured. Figure 64 shows the transfer signal sequence for Motorola SPI format with SPO=1, SPH=1, and covers both single continuous transfers. SSPCLKOUT/ SSPCLKIN SSPFSSOUT/...

  • Page 376: National Semiconductor Microwire Frame Format

    If the PrimeCell SSP is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSPFSSOUT master signal being driven LOW. The nSSPOE line is driven LOW, enabling the master SSPTXD output pad. After an additional one half SSPCLKOUT period, both master and slave data are enabled onto their respective transmission lines.
  • Page 377 returned data is 4 to 16 bits in length, making the total frame length in the range of 13-25 bits. In this configuration, during idle periods: • SSPCLKOUT is forced LOW • SSPFSSOUT is forced HIGH • the transmit data line, SSPTXD, is arbitrarily forced LOW •...

  • Page 378: Master And Slave Configurations

    SSPCLKOUT/ SSPCLKIN SSPFSSOUT/ SSPFSSIN SSPTXD 4 to 16 bits 8-bit control output data SSPRXD nSSPOE Figure 66. National Semiconductor Microwire frame format, continuous transfers Master and Slave configurations Figure 67 shows how a PrimeCell SSP (PL022) configured as master, interfaces to a Motorola SPI slave.

  • Page 379: Ssp Flow Chart

    Figure 68. SPI master coupled to a PrimeCell SSP slave SSP Flow chart Figure 69 shows how to setting TI or Microwire mode. TI or Microwire TI or Microwire Data Send Data Send to Slave to Master (Master mode) (Slave mode) SerialClockRate Setting (Slave Output...

  • Page 380: Ssp0 Registers (Base Address : 0X4000_A000)

    Figure 70 shows how to setting SPI mode. SPI Data Send SPI Data Send to Slave to Master (Master mode) (Slave mode) SerialClockRate Setting (choose 0~255) CPHA == 0 ? CPHA == 0 ? Captured 1 Edge Captured 2 Edge Captured 1 Edge Captured 2 Edge CPHA == 0 ?
  • Page 381 [3:0] DSS – Data size select: 0000 : reserved, undefined operation 0001 : reserved, undefined operation 0010 : reserved, undefined operation 0011 : 4-bit data 0100 : 5-bit data 0101 : 6-bit data 0110 : 7-bit data 0111 : 8-bit data 1000 : 9-bit data 1001 : 10-bit data 1010 : 11-bit data...

  • Page 382: Ssp0 Control Register 1 (Ssp0Cr1)

    SSP0 Control register 1 (SSP0CR1) Address offset: 0x0004 Reset value: 0x0000_0000 [0] LBM – Loop back mode: 0 : normal serial port operation enabled 1 : output of transmit serial shifter is connected to input of receive serial shifter internally [1] SSE –...

  • Page 383: Ssp0 Status Register (Ssp0Sr)

    Data [15:0] DATA – Transmit/Receive FIFO: Read: Read: receive FIFO. Write: transmit FIFO. You must right-justify data when the SSP0 is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies.

  • Page 384: Ssp0 Clock Prescale Register (Ssp0Cpsr)

    1 : SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. SSP0 Clock prescale register (SSP0CPSR) Address offset: 0x0010 Reset value: 0x0000_00000 CPSDVSR [7:0] CPSDVSR – Clock prescale divisor This must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads.

  • Page 385: Ssp0 Raw Interrupt Status Register (Ssp0Ris)

    1 : Receive FIFO not empty and no read prior to timeout period interrupt is not masked. [2] RXIM – Receive FIFO interrupt mask: 0 : Receive FIFO half full or less condition interrupt is masked. 1 : Receive FIFO half full or less condition interrupt is not masked. [3] TXIM –...

  • Page 386: Ssp0 Interrupt Clear Register (Ssp0Icr)

    [0] RORMIS – Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt [1] RTMIS – Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt [2] RXMIS – Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt [3] TXMIS –...
  • Page 387 [0] RXDMAE – Receive DMA Enable: 0 : DMA for the receive FIFO is disabled. 1 : DMA for the receive FIFO is enabled. [1] TXDMAE – Transmit DMA Enable: 0 : DMA for the transmit FIFO is disabled. 1 : DMA for the transmit FIFO is enabled. 387 / 399 W7500x Reference Manual Version1.1.0...

  • Page 388: Register Map

    27.5 Register map The following Table 38 summarizes the SSP0 registers. Table 38 SSP0 register map and reset values 388 / 399 W7500x Reference Manual Version1.1.0...

  • Page 389: Ssp1 Registers (Base Address : 0X4000_B000)

    27.6 SSP1 Registers (Base Address : 0x4000_B000) This section describes the SSP0 registers. SSP1 Control register 0 (SSP1CR0) Address offset: 0x0000 Reset value: 0x0000_0000 [3:0] DSS – Data size select: 0000 : reserved, undefined operation 0001 : reserved, undefined operation 0010 : reserved, undefined operation 0011 : 4-bit data 0100 : 5-bit data...

  • Page 390: Ssp1 Control Register 1 (Ssp1Cr1)

    This is applicable to Motorola SPI frame format only. [15:8] SCR – Serial clock rate The value SCR is used to generate the transmit and receive bit rate of the SSP. The bit rate is: fSSPCLK / (CPSDVSR * (1 + SCR)) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255.
  • Page 391 1 : SSP1 must not drive the SSPTXD output in slave mode. 391 / 399 W7500x Reference Manual Version1.1.0...

  • Page 392: Ssp1 Data Register (Ssp1Dr)

    SSP1 Data register (SSP1DR) Address offset: 0x0008 Reset value: 0x0000_0000 Data [15:0] DATA – Transmit/Receive FIFO: Read: Read: receive FIFO. Write: transmit FIFO. You must right-justify data when the SSP1 is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies.

  • Page 393: Ssp1 Clock Prescale Register (Ssp1Cpsr)

    [3] RFF – Receive FIFO full, RO: 0 : Receive FIFO is not full. 1 : Receive FIFO is full. [4] BSY – SSP busy flag, RO: 0 : SSP is idle.No effect 1 : SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty.

  • Page 394: Ssp1 Raw Interrupt Status Register (Ssp1Ris)

    1 : Receive FIFO written to while full condition interrupt is not masked. [1] RTIM – Receive timeout interrupt mask: 0 : Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 : Receive FIFO not empty and no read prior to timeout period interrupt is not masked.

  • Page 395: Ssp1 Interrupt Clear Register (Ssp1Icr)

    [0] RORMIS – Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt [1] RTMIS – Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt [2] RXMIS – Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt [3] TXMIS –...
  • Page 396 [0] RXDMAE – Receive DMA Enable: 0 : DMA for the receive FIFO is disabled. 1 : DMA for the receive FIFO is enabled. [1] TXDMAE – Transmit DMA Enable: 0 : DMA for the transmit FIFO is disabled. 1 : DMA for the transmit FIFO is enabled. 396 / 399 W7500x Reference Manual Version1.1.0...

  • Page 397: Register Map

    27.7 Register map The following Table 39 summarizes the SSP1 registers. Table 39 SSP1 register map and reset values 397 / 399 W7500x Reference Manual Version1.1.0...

  • Page 398: Document History Information

    Document History Information Version Date Descriptions Ver. 1.0.0 18SEP2017 Initial Release Ver. 1.0.1 12OCT2017 Edit Flash Chapter. Ver. 1.0.2 26OCT2017 Edit GPIO,PADCON Register and added Open Drain function Ver. 1.0.3 27OCT2017 TCKCNTR, RTR, Sn_RTR, Sn_KATMR Additional description added. Ver. 1.0.4 09NOV2017 Edit PADCON register description CS,DS inverted value.
  • Page 399 Copyright Notice Copyright 2018 WIZnet Co., Ltd. All Rights Reserved. Technical Support: https://forum.wizwiki.io/ Sales & Distribution: sales@wiznet.io For more information, visit our website at http://www.wiznet.io/ 399 / 399 W7500x Reference Manual Version1.1.0...

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