Ssp0 Interrupt Clear Register (Ssp0Icr); Ssp0 Dma Control Register, (Ssp0Dmacr) - Wiznet W7500 Reference Manual

15 14 13 12
res res res res
[0] RORMIS – Gives the receive over run masked interrupt status, after masking, of
the SSPRORINTR interrupt
[1] RTMIS – Gives the receive timeout masked interrupt state, after masking, of the
SSPRTINTR interrupt
[2] RXMIS – Gives the receive FIFO masked interrupt state, after masking, of the
SSPRXINTR interrupt
[3] TXMIS – Gives the transmit FIFO masked interrupt state, after masking, of the
SSPTXINTR interrupt
23.4.9

SSP0 Interrupt clear register (SSP0ICR)

Address offset: 0x0020
Reset value: 0x0000_00000
31 30 29 28
res res res res
15 14 13 12
res res res res
[0] RORICS – Clears the SSPRORINTR interrupt
[1] RTIC – Clears the SSPRTINTR interrupt
23.4.10

SSP0 DMA control register, (SSP0DMACR)

Address offset: 0x0024
Reset value: 0x0000_00000
31 30 29 28
W7500 Datasheet Version1.0.0
11 10 9 8
res res res res
27 26 25 24
res res res res
11 10 9 8
res res res res
27 26 25 24
7 6 5 4
res res res res
23 22 21 20
res res res res
7 6 5 4
res res res res
23 22 21 20
3 2 1 0
TXM RXM RTM ROR
IS IS IS MIS
R/W R/W R/W R/W
19 18 17 16
res res res res
3 2 1 0
ROR
res res RTIC
IC
R/W R/W
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