Timer0_1 Interrupt Clear Register (Dualtimer0_1Timerintclr); Timer0_1 Raw Interrupt Status Register (Dualtimer0_1Timerris) - Wiznet W7500 Reference Manual

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Table of Contents

[0] OC – One-shot Count

0 : Wrapping mode, default.

1 : One-shot mode.

[1] TS – Timer Size

0 : 16-bit counter, default.

1 : 32-bit counter.

[3:2] TP – Timer Prescale.

00 : 0 stages of prescale, clock is divided by 1, default.

01 : 4 stages of prescale, clock is divided by 16.

10 : 8 stages of prescale, clock is divided by 256.

11 : Undefined, do not use.

[5] IE – Interrupt Enable.

0 : Timer Interrupt disable.

1 : Timer Interrupt enabled, default.

[6] TM – Timer Mode.

0 : Timer is in free-running mode, default.

1 : Timer is in periodic mode.

[7] TE – Timer Enable.

0 : Timer disabled, default.

1 : Timer enabled.

Timer0_1 Interrupt Clear Register

(DUALTIMER0_1TimerIntClr)

Base address : 0x4000_1020

Address offset : 0x0C

[0] IC – Interrupt Clear

Set to the this register clears the interrupt output from the counter.

Timer0_1 Raw Interrupt Status Register

(DUALTIMER0_1TimerRIS)

Base address : 0x4000_1020

W7500 Datasheet Version1.0.0