Slave Address; Read/Write Bit; Figure 49. Start And Stop Conditions; Figure 50. Restart Condition - Wiznet W7500 Reference Manual

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START and STOP conditions are always generated by the master.

This bus is considered to be again a certain time after the STOP condition. The bus stays

busy if a Repeated START is generated instead of a STOP condition.

21.3.3.2 RESTART Condition

Slave address

The SDA line must be eight bits long.

Each byte must be followed by an Acknowledge bit.

Slave Address

This address is seven bits followed by an eight bit which is a data direction bit(R/W) :

„0‟ indicates a WRITE, „1‟ indicates a READ

There are two methods of setting data direction bit by I2Cx_CTR.

The 32-bits I2Cx_CTR is reconfigured with COREEN, INTEREN, MODE, ADDR10, CTRRWN,

W7500 Datasheet Version1.0.0

START Condition

STOP Condition

RESTART Condition