Wiznet W7500 Reference Manual page 435

Internet offload processor

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Table of Contents

[0] ACKR – Acknowledge Receive

[1] SRW – Slave Read/Write

This bit set by hardware when receive status.

[2] TO – Time Out

This bit set by hardware when the timeout occur by I2C1_TST register setting value

[3] Reserved, must be kept at reset value

[4] SB – Slave Busy (Slave mode)

This bit set by hardware when the slave address and R/W bit have been transmitted

and an acknowledgment bit has been received (waiting for data).

[5] SA – Slave Address Transmit (master mode)

This bit set by hardware when the Slave address have been transmitted.

[6] BT – Byte Transmit

This bit set by hardware when the 1byte data was transmitted except ack signal.

[7] ACKT – Acknowledge Transmit

This bit set by hardware when the ack signal was transmitted.

[8] RX – Receive status

[9] TX – Transmit status

This bit set by hardware when the data is transmitting and the data to be

transmitted must be written in the I2C1_TXDR register.

[31:10] Reserved, must be kept at reset value

W7500 Datasheet Version1.0.0