I2C1 Interrupt Status Register(I2C1_Isr); I2C1 Interrupt Status Clear Register(I2C1_Iscr) - Wiznet W7500 Reference Manual

21.6.9

I2C1 Interrupt Status Register(I2C1_ISR)

Address offset: 0x20
Reset value: 0x0000_0000
31 30 29 28
res res res res
15 14 13 12
res res res res
[0]ACK_TXE – Acknowledge Transmit status
[1]ACK_RXE – Acknowledge Receive status
[2]TOE - Timeout detection flag
[3]STOE– STOP detection flag (master mode)
This flag is set by hardware when a STOP condition is detected on the bus and the
peripheral is involved in this transfer: – either as a master, provided that the STOP
condition is generated by the peripheral. – or as a slave, provided that the peripheral
has been addressed previously during this transfer.
[4] STAE – START detection flag (master mode)
This flag is set by hardware when a START condition is detected on the bus and the
peripheral is involved in this transfer: – either as a master, provided that the START
condition is generated by the peripheral. – or as a slave, provided that the peripheral
has been addressed previously during this transfer.
[31:5] Reserved, must be kept at reset value
21.6.10

I2C1 Interrupt Status Clear Register(I2C1_ISCR)

Address offset: 0x24
Reset value: 0x0000_0000
W7500 Datasheet Version1.0.0
27 26 25 24
res res res res
11 10 9 8
res res res res
23 22 21 20
res res res res
7 6 5 4
res res res
STAE
R
19 18 17
res res res
3 2 1
STOE TOE ACK_RXE
R R R
438 / 512
16
res
0
ACK_TXE
R