Wiznet W7500 Reference Manual page 5

10.4 Registers (Base address : 0x4100_1000) ................................................ 95
10.4.1 OSC power down register (OSC_PDR) ........................................... 95
10.4.2 PLL power down register (PLL_PDR) ............................................ 95
10.4.3 PLL frequency calculating register (PLL_FCR) ................................. 95
10.4.4 PLL output enable register (PLL_OER) .......................................... 96
10.4.5 PLL bypass register (PLL_BPR) ................................................... 96
10.4.6 PLL input clock source select register (PLL_IFSR) ............................ 97
10.4.7 FCLK source select register (FCLK_SSR) ........................................ 97
10.4.8 FCLK prescale value select register (FCLK_PVSR) ............................ 98
10.4.9 SSPCLK source select register (SSPCLK_SSR) .................................. 98
10.4.10 SSPCLK prescale value select register (SSPCLK_PVSR) ....................... 99
10.4.11 ADCCLK source select register (ADCCLK_SSR) ................................. 99
10.4.12 ADCCLK prescale value select register (ADCCLK_PVSR) .................... 100
10.4.13 TIMER0CLK source select register (TIMER0CLK_SSR) ........................ 100
10.4.14 TIMER0CLK prescale value select register (TIMER0CLK_PVSR) ............ 100
10.4.15 TIMER1CLK source select register (TIMER1CLK_SSR) ........................ 101
10.4.16 TIMER1CLK prescale value select register (TIMER1CLK_PVSR) ............ 101
10.4.17 PWM0CLK source select register (PWM0CLK_SSR) ........................... 102
10.4.18 PWM0CLK prescale value select register (PWM0CLK_PVSR) ................ 103
10.4.19 PWM1CLK source select register (PWM1CLK_SSR) ........................... 103
10.4.20 PWM1CLK prescale value select register (PWM1CLK_PVSR) ................ 104
10.4.21 PWM2CLK source select register (PWM2CLK_SSR) ........................... 104
10.4.22 PWM2CLK prescale value select register (PWM2CLK_PVSR) ................ 105
10.4.23 PWM3CLK source select register (PWM3CLK_SSR) ........................... 105
10.4.24 PWM3CLK prescale value select register (PWM3CLK_PVSR) ................ 106
10.4.25 PWM4CLK source select register (PWM4CLK_SSR) ........................... 106
10.4.26 PWM4CLK prescale value select register (PWM4CLK_PVSR) ................ 107
10.4.27 PWM5CLK source select register (PWM5CLK_SSR) ........................... 107
10.4.28 PWM5CLK prescale value select register (PWM5CLK_PVSR) ................ 108
10.4.29 PWM6CLK source select register (PWM6CLK_SSR) ........................... 108
10.4.30 PWM6CLK prescale value select register (PWM6CLK_PVSR) ................ 109
10.4.31 PWM7CLK source select register (PWM7CLK_SSR) ........................... 109
10.4.32 PWM7CLK prescale value select register (PWM7CLK_PVSR) ................ 110
10.4.33 WDOGCLK High Speed source select register (WDOGCLK_HS_SSR) ....... 110
10.4.34 WDOGCLK High Speed prescale value select register (WDOGCLK_HS_PVSR)
111
10.4.35 UARTCLK source select register (UARTCLK_SSR) ............................. 111
10.4.36 UARTCLK prescale value select register (UARTCLK_PVSR) ................. 112
10.4.37 MIICLK enable control register (MIICLK_ECR) ................................. 112
W7500 Datasheet Version1.0.0
5 / 512