Gpioa Interrupt Enable Clear Register(Gpioa_ Intenclr); Gpioa Interrupt Type Set Register(Gpioa_ Inttypeset) - Wiznet W7500 Reference Manual

31 30 29
res res res
15 14 13
IES15 IES14 IES13
R/W R/W R/W
[15:0] IESy(y = 0..15)
WRITE as :
„0‟ is no effect
„1‟ is sets the interrupt enable bit
READ as :
„0‟ is indicates the interrupt disable
„1‟ is indicates the interrupt enable
15.4.6

GPIOA Interrupt Enable Clear Register(GPIOA_ INTENCLR)

Address offset: 0x0024
Reset value: 0x----
31 30 29
res res res
15 14 13
IEC15 IEC14 IEC13
R/W R/W R/W
[15:0] IECy(y = 0..15)
WRITE as :
„0‟ is no effect
„1‟ is clears the interrupt enable bit
READ as :
„0‟ is indicates the interrupt disable
„1‟ is indicates the interrupt enable
15.4.7

GPIOA Interrupt Type Set Register(GPIOA_ INTTYPESET)

Address offset: 0x0028
Reset value: 0x----
W7500 Datasheet Version1.0.0
28 27 26
res res res
12 11 10
IES12 IES11 IES10
R/W R/W R/W
28 27 26
res res res
12 11 10
IEC12 IEC11 IEC10
R/W R/W R/W
25 24 23 22
res res res res
9 8 7 6
IES9 IES8 IES7 IES6
R/W R/W R/W R/W
25 24 23 22
res res res res
9 8 7 6
IEC9 IEC8 IEC7 IEC6
R/W R/W R/W R/W
21 20 19 18
res res res res
5 4 3 2
IES5 IES4 IES3 IES2
R/W R/W R/W R/W
21 20 19 18
res res res res
5 4 3 2
IEC5 IEC4 IEC3 IEC2
R/W R/W R/W R/W
237 / 512
17 16
res res
1 0
IES1 IES0
R/W R/W
17 16
res res
1 0
IEC1 IEC0
R/W R/W