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CTREN bit select the R/W – a „Zero‟ indicates the slave address bit 0, a „one‟ indicates a
CTRRWN bit.
CTREN bit select the R/W – a „Zero‟ indicates the slave address bit 0, a „one‟ indicates a
CTRRWN bit.
21.3.6
Acknowledge(ACK) and Not Acknowledge(NACK)
The acknowledge bit takes place after every bytes. The acknowledge bit allows the receiver
to signal the transmitter that the byte was successfully received and another byte may be
sent. The master generates all clock pulses, including acknowledge ninth clock.
21.3.7
Data transfer
The data transfer is managed through the shift, transmit data, and receive data registers.
Data transfers follow the format shown in Figure 52. After START condition, a Slave address
is transmitted. If CTREN bit in the I2Cx_CTR register is enable, LSB of Slave address (bit 0) is
superseded by value of CTRRWN bit in the I2Cx_CTR register.
If CTREN bit in the I2Cx_CTR register is disable, LSB of slave address is used for Read/Write
operation.
Slave addr
SDA
SCL
S
Figure 52. Complete Data Transfer with a 7-bit slave address
21.3.8
Operating Modes
The interface can operate in one of four following:
Master Transmitter Mode
Master Receiver Mode
Slave Transmitter Mode
Slave Receiver Mode
By default, it operates in slave mode. The interface switches from slave to master when it
generates the mode bit in the I2Cx_CTR. And COREEN bit in the I2Cx_CTR must be switched
from 1 to 0.
W7500 Datasheet Version1.0.0
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