Uart0Fr (Uart0 Flag Register) - Wiznet W7500 Reference Manual

The UART0RSR/ECR is the receive status register/error clear register.
Receive status can also be read from the UART0RSR register.
A write to the UART0ECR register clears the framing, parity, break, and overrun errors.
31 30 29 28
res res res res
15 14 13 12
res res res res
[3] OE – Overrun error
This bit is set to 1 if data is received and the FIFO is already full.
This bit is cleared to 0 by a write to UART0ECR
[2] BE – Break error
This bit is cleared to 0 by a write to UART0ECR
[1] PE – Parity error
When set to 1, it indicates that the parity of the received data character does not
match
the parity that the EPS and SPS bits in the line control register, UARTLCR_H select
This bit is cleared to 0 by a write to UART0ECR
[0] FE – Framing error
When set to 1, in indicates that the received character didn‟t have a valid stop bit
This bit is cleared to 0 by a write to UART0ECR
22.4.3

UART0FR (UART0 Flag Register)

Address offset: 0x0018
Reset value: 0bx11000xxx
31 30 29 28
res res res res
15 14 13 12
res res res res
[8] RI – Ring indicator
This bit is the complement of the UART ring indicator, UART0RI.
1: When nUART0RI is LOW
W7500 Datasheet Version1.0.0
27 26 25 24
res res res res
11 10 9 8
res res res res
27 26 25 24
res res res res
11 10 9 8
res res res
RI
R
23 22 21 20
res res res res
7 6 5 4
res res res res
23 22 21 20
res res res res
7 6 5 4
TXFE RXFF TXFF RXFE
R R R R
19 18 17 16
res res res res
3 2 1 0
OE BE PE FE
19 18 17 16
res res res res
3 2 1 0
BUSY DCD DSR CTS
R R R R
449 / 512