Ssp1 Data Register (Ssp1Dr); Ssp1 Status Register (Ssp1Sr) - Wiznet W7500 Reference Manual

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SSP1 Data register (SSP1DR)

Address offset: 0x0008

Reset value: 0x0000_0000

[15:0] DATA – Transmit/Receive FIFO:

Read: Read: receive FIFO.

Write: transmit FIFO.

You must right-justify data when the SSP1 is programmed for a data size that is less

than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic

automatically right-justifies.

Address offset: 0x000C

Reset value: 0x0000_0003

[0] TFE – Transmit FIFO empty, RO

0 : Transmit FIFO is not empty.

1 : Transmit FIFO is empty.

[1] TNF – Transmit FIFO not full, RO:

0 : Transmit FIFO is full.

1 : Transmit FIFO is not full.

[2] RNE – Receive FIFO not empty, RO:

0 : Receive FIFO is empty.

1 : Receive FIFO is not empty.

W7500 Datasheet Version1.0.0