I2C1 Command Register(I2C1_Cmdr); I2C1 Status Register(I2C1_Sr) - Wiznet W7500 Reference Manual

21.6.3

I2C1 Command Register(I2C1_CMDR)

Address offset: 0x08
Reset value: 0x0000_0000
31 30 29 28
res res res res
15 14 13 12
res res res res
[3:0] Reserved, must be kept at reset value
[4] RESTA – Repeat start condition (master mode)
0: disable Repeat start
1: enable Repeat start
[5] ACK – Acknowledgement condition (master mode)
0: NACK condition
1: ACK condition
[6] STO – Stop Condition (master mode)
0: disable condition
1: enable condition
[7] STA – Start Condition (master mode)
0: disable Start condition
1: enable Start condition
[31:8] Reserved, must be kept at reset value
21.6.4

I2C1 Status Register(I2C1_SR)

Address offset: 0x0C
Reset value: 0x0000_0000
W7500 Datasheet Version1.0.0
27 26 25 24
res res res res
11 10 9 8
res res res res
23 22 21 20
res res res res
7 6 5
STA STO ACK RESTA
R/W R/W R/W R/W
19 18 17
res res res
4 3 2 1
res res res
434 / 512
16
res
0
res